Memory map: Difference between revisions
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== Memory Map accesses ==
The whole memory map is implemented by RCP, as the VR4300 only talks directly to RCP. The bus between VR4300 and RCP is called [[SysAD Interface|SysAD]]. The RCP behaves differently with different access sizes depending on the specific area of the map and the subcomponent in charge of implementing it.
The SysAD bus is described at the hardware level in the dedicated page, but to understand the effects on memory map it is sufficient to understand how data is marshalled for reads and writes. Since SysAD is a 32-bit bus, 32-bit accesses are the "native" ones, and the others are made to work around a 32-bit data exchange.
* Reads: VR4300 puts the address on the bus and the size of the access (8, 16, 32, 64). The RCP typically returns a full (aligned) 32-bit word address (or two, in case of a 64-bit read), from which the VR4300 extracts the correct portion. For instance, when reading 8-bit from address 0x0000'0001, the RCP will put on the bus the 32-bit values at 0x0000'0000 - 0x0000'0003, and the VR4300 will then just isolate the requested 8 bits.
* Writes: VR4300 puts the address on the bus, the size of the access, and then the 32-bit value to be written. When the access is made using 8 or 16 bits, the value on the bus is prepared to match with the aligned 32-bit address. This is the same of what happens for reads, but this time it is the VR4300 to prepare the data. For instance, if register <code>S0=0x1234'5678</code>, <code>A0=0x0000'0001</code> and the opcode <code>SB S0, 0(A0)</code> is run, the VR4300 puts on the bus the value <code>S0 << 24</code>, that is <code>0x5678'0000</code>. It is then up to the RCP to see that, since the address is <code>0x0000'0001</code>, it needs to isolate the the second byte <code>0x78</code>. So even if it is a 8-bit write opcode, other bits of the register <code>S0</code> "leak" on the bus.
Notice that misaligned address are forbidden by MIPS architecture and they will result in an Address Exception. So all accesses that go through the memory map are always aligned to the access size (eg: aligned to 2 bytes for 16-bit reads/writes).
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The accesses in this area are handled by RCP itself without going to an external bus, and are dispatched internally to the correct subsystem. Access to a register might optionally stall the VR4300 if the subsystem is designed to do so (eg: to perform a long blocking operation on write), but in general for standard registers, they are immediate and take only 1 PClock cycle.
Accesses in this area are affected by a simplified hardware implementation of the RCP SysAD bus, so '''''access size is ignored'''''. This means that:
* Reads: RCP will ignore the requested access size and will just put the requested 32-bit word on the bus. Luckily, this is the correct behavior for 8-bit and 16-bit accesses (as explained above), so the VR4300 will be able to extract the correct portion. For 64-bit accesses, the 32-bit word stays on the bus for two cycles, so basically the VR4300 will see a 64-bit value which contains the 32-bit value duplicated in both MSB and LSB.
* Writes: RCP will ignore the requested access size and just write the word that was put on the bus directly into the hardware register. For 8-bit and 16-bit accesses, this means that the shifted value prepared by the VR4300 is the one that will be written verbatim. Reprising the example above, if <code>S0=0x1234'5678</code>, <code>A0=0x0460'0011</code>, running <code>SB S0, 0(A0)</code> will write the value <code>0x5678'0000</code> to the RCP hardware register <code>0x0460'0010</code>. For 64-bit accesses, as they are written on the bus MSB-first, the RCP will write the MSB to the hardware register, ignoring the LSB.
=== Ranges 0x0500'0000 - 0x1FBF'FFFF and 0x1FD00000 - 0xFFFF'FFFF (External SysAD bus via PI) ===
All accesses made by the VR4300 in these ranges are forward externally by RCP on the external bus via PI. This allows the CPU to access external devices like the cartridge ROM and SRAM.
Accesses in this area are affected by the same simplified SysAD implementation described above, so '''access size is ignored.''' The effect is the same described before.
Moreover, there are two important additional details:
* All writes are performed '''asynchronously''' by the PI. Making a write in this area will in fact just cause the PI to latch the value internally, and release the VR4300 immediately. The write will then happen in background. The status of the ongoing write will be reflected by the PI "I/O busy" status bit, which will be set to 1 until the write is finalized. For further information on this, please check the [[Peripheral Interface|PI page]].
* All external accesses are made by RCP through a 16-bit bus. Given that the RCP only knows of 32-bit accesses (as access size is ignored), this means that each read or write performed by the VR4300 will cause exactly two reads or two writes on the 16-bit bus: first the MSB at the address specified by the CPU (ignoring bit 0, so that the address is aligned to 16 bit), then the LSB at address+2. This might seem a small implementation detail, but it does actually cause an important and visible bug. For instance, if the VR4300 requests a 16-bit read at address <code>0x1000'0002</code>, the RCP (that ignores access sizes) will do two 16-bit reads on the cartridge bus at <code>0x1000'0002</code> and <code>0x1000'0004</code>, and will put on the SysAD bus the 32-bit word at <code>0x1000'0002 - 0x1000'0005</code>. This is a violation of the SysAD protocol explained above: in fact, the RCP should have put on the bus the 32-bit word at <code>0x1000'0000 - 0x1000'0003</code> instead. Because of this, effectively a 16-bit read at <code>0x1000'0002</code> returns the 16-bit word at <code>0x1000'0004</code> instead.
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