Memory map: Difference between revisions

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{| class="wikitable"
!style="width: 10%"|Bus / Device
! colspan=2 | Address Range !!style="width: 15%"| Name !! Description
!Mirror mask!! style="width: 15%" | Name !! Description
|-
| rowspan="3" |RDRAM
| 0x00000000 || 0x03EFFFFF
| 0x00000000 || 0x03EFFFFF || [[RDRAM]] memory-space || RDRAM memory. See [[RDRAM_Interface#Memory_addressing]] and [[RDRAM#RDRAM_addressing]] for details about their mapping.
|-
| 0x03F00000 || 0x03F7FFFF
| 0x03F00000 || 0x03F7FFFF 0x00000000|| [[RDRAM#Registers|RDRAM Registers]] || RDRAM registers. See [[RDRAM_Interface#Memory_addressing]] and [[RDRAM#RDRAM_addressing]] for details about their mapping.
|-
| 0x03F80000 || 0x03FFFFFF
| 0x03F80000 || 0x03FFFFFF 0x00000000|| [[RDRAM#Registers|RDRAM Registers]] (broadcast) || Write-only. All connected RDRAM will act on this register write request. See [[RDRAM_Interface#Memory_addressing]] and [[RDRAM#RDRAM_addressing]] for details.
|-
| rowspan="1413" |RCP
| 0x04000000 || 0x04000FFF || [[Reality Signal Processor/Interface#DMEM and IMEM|RSP DMEM]]|| RSP Data Memory
|0x0003EFFF|| [[Reality Signal Processor/Interface#DMEM and IMEM|RSP DMEM]]|| RSP Data Memory
|-
| 0x04001000 || 0x04001FFF || [[Reality Signal Processor/Interface#DMEM and IMEM|RSP IMEM]]|| RSP Instruction Memory
|0x0003EFFF|| [[Reality Signal Processor/Interface#DMEM and IMEM|RSP IMEM]]|| RSP Instruction Memory
|-
| 0x04040000 || 0x040BFFFF
| 0x04002000 || 0x0403FFFF || RSP DMEM/IMEM Mirrors || Mirrors of DMEM and IMEM (repeat every 8Kb)
| 0x04040000 || 0x040BFFFF ?|| [[RSP|RSP Registers]] || RSP DMAs, status, semaphore, program counter, IMEM BIST status▼
|-
▲| 0x04040000 || 0x040BFFFF || [[RSP|RSP Registers]] || RSP DMAs, status, semaphore, program counter, IMEM BIST status
|-
|0x040C0000
|0x040FFFFF
|0x00000000
|Unmapped
|This area is completely ignored by the RCP. Any access in this area will freeze the CPU as the RCP will ignore the read/write and the CPU will never receive a reply.
|-
| 0x04100000 || 0x041FFFFF
| 0x04100000 || 0x041FFFFF 0x001FFFFC|| [[Reality Display Processor|RDP Command Registers]]|| RDP DMAs, clock counters for: clock, buffer busy, pipe busy, and TMEM load
|-
| 0x04200000 || 0x042FFFFF || RDP Span Registers || TMEM BIST status, DP Span testing mode
|?|| RDP Span Registers || TMEM BIST status, DP Span testing mode
|-
| 0x04300000 || 0x043FFFFF
| 0x04300000 || 0x043FFFFF ?|| [[MIPS Interface]] (MI) || Init mode, ebus test mode, RDRAM register mode, hardware version, interrupt status, interrupt masks
|-
| 0x04400000 || 0x044FFFFF || [[Video Interface]] (VI) || Video control registers
|?|| [[Video Interface]] (VI) || Video control registers
|-
| 0x04500000 || 0x045FFFFF || [[Audio Interface]] (AI) || Audio DMAs, Audio DAC clock divider
|?|| [[Audio Interface]] (AI) || Audio DMAs, Audio DAC clock divider
|-
| 0x04600000 || 0x046FFFFF
| 0x04600000 || 0x046FFFFF ?|| [[Peripheral Interface]] (PI) || Cartridge port DMAs, status, Domain 1 and 2 speed/latency/page-size controls
|-
| 0x04700000 || 0x047FFFFF
| 0x04700000 || 0x047FFFFF ?|| [[RDRAM Interface]] (RI) || Operating mode, current load, refresh/select config, latency, error and bank status
|-
| 0x04800000 || 0x048FFFFF || [[Serial Interface]] (SI) || SI DMAs, PIF status
|?|| [[Serial Interface]] (SI) || SI DMAs, PIF status
|-
| 0x04900000 || 0x04FFFFFF
| 0x04900000 || 0x04FFFFFF 0x00000000|| Unmapped || This area is completely ignored by the RCP. Any access in this area will freeze the CPU as the RCP will ignore the read/write and the CPU will never receive a reply.
|-
| rowspan="4" |PI external bus
| 0x05000000 || 0x05FFFFFF || N64DD Registers || Contains the N64DD I/O registers.
|?|| N64DD Registers || Contains the N64DD I/O registers.
Accesses here are forwarded to the [[PI|PI bus]], with the same address within the PI address space, using the "Domain 1" configuration set.
When not present, this is a [[Peripheral Interface#Open bus behavior|PI open bus]] area.
|-
| 0x06000000 || 0x07FFFFFF
| 0x06000000 || 0x07FFFFFF ?|| N64DD IPL ROM || Contains the N64DD ROM used during boot, sometimes called IPL4. This is executed whenever the console is turned on with a N64DD connected, in place of the [[PIF-NUS#Console startup|IPL3]].
Accesses here are forwarded to the [[PI|PI bus]], with the same address within the PI address space, using the "Domain 1" configuration set.
When not present, this is a [[Peripheral Interface#Open bus behavior|PI open bus]] area.
|-
| 0x08000000 || 0x0FFFFFFF
| 0x08000000 || 0x0FFFFFFF ?|| Cartridge SRAM/FlashRAM || When the cartridge uses SRAM or FlashRAM for save games, this is conventionally exposed at this address range.
Accesses here are forwarded to the [[PI|PI bus]], with the same address within the PI address space, using the "Domain 2" configuration set. This is one of the few address ranges which are in Domain 2, probably because it is common to access SRAM/FlashRAM with a different (slower) protocol.
When not present, this is a [[Peripheral Interface#Open bus behavior|PI open bus]] area.
|-
| 0x10000000 || 0x1FBFFFFF
| 0x10000000 || 0x1FBFFFFF 0x00000000|| [[ROM Header|Cartridge ROM]]|| The cartridges expose the ROM at this address. Normally, games will load assets and overlays via PI DMA for speed concerns, but the ROM is nonetheless memory mapped. Notice that cache accesses are not allowed here (and in all PI external bus accesses, see below for details), so while it is possible to run code directly from ROM, it will be extremely slow as it would not leverage the instruction cache.
Accesses here are forwarded to the [[PI|PI bus]], with the same address within the PI address space, using the "Domain 1" configuration set.
When not present (eg: when booting a disk-only N64DD game without a cartridge), this is a [[Peripheral Interface#Open bus behavior|PI open bus]] area.
|-
| rowspan="3" |SI external bus
| 0x1FC00000 || 0x1FC007BF || PIF ROM ([[Initial Program Load|IPL1/2]]) || Executed on boot
|?|| PIF ROM ([[Initial Program Load|IPL1/2]]) || Executed on boot
|-
| 0x1FC007C0 || 0x1FC007FF
| 0x1FC007C0 || 0x1FC007FF ?|| [[PIF-NUS|PIF]] RAM || Controller and EEPROM communication, and during IPL1/2 is used to read startup data from the PIF
|-
| 0x1FC00800 || 0x1FCFFFFF || Reserved || Unknown usage
|?|| Reserved || Unknown usage
|-
| rowspan="2" |PI external bus
| 0x1FD00000 || 0x1FFFFFFF
| 0x1FD00000 || 0x1FFFFFFF 0x00000000|| Unused || Accesses here are forwarded to the [[PI|PI bus]], with the same address within the PI address space, using the "Domain 1" configuration set.
No known PI device uses this range, so it will normally be a [[Peripheral Interface#Open bus behavior|PI open bus]] area.
|-
|0x20000000
|0x7FFFFFFF
|0x00000000
|Unused
|Accesses here are forwarded to the [[PI|PI bus]], with the same address within the PI address space, using the "Domain 1" configuration set.
Line 102 ⟶ 126:
|-
|
| 0x80000000 || 0xFFFFFFFF
| 0x80000000 || 0xFFFFFFFF 0x00000000|| Unmapped || This area is completely ignored by the RCP. Any access in this area will freeze the CPU as the RCP will ignore the read/write and the CPU will never receive a reply.
|}
 
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