Memory map: Difference between revisions

== Physical Memory Map accesses ==

The wholephysical memory map is implemented by RCP, as the VR4300 only talks directly to RCP. The bus between VR4300 and RCP is called [[SysAD Interface|SysAD]]. The RCP behaves differently with different access sizes depending on the specific area of the map and the subcomponent in charge of implementing it.

The SysAD bus is described at the hardware level in the dedicated[[SysAD Interface|SysAD page]], but to understand the effects on memory map it is sufficient to understand how data is marshalled for reads and writes. Since SysAD is a 32-bit bus, 32-bit accesses are the "native" ones, and the othersother access sizes are made toin a weird way workbuilt aroundupon a 32-bit data exchange.

* Reads: VR4300 puts the address on the bus and the size of the access (8, 16, 32, 64). The RCP typically returns a full (aligned) 32-bit word address (or two, in case of a 64-bit read), from which the VR4300 extracts the correct portion. For instance, when reading 8-bit from address <code>0x0000'0001</code>, the RCP will put on the bus the 32-bit values at <code>0x0000'0000 - 0x0000'0003</code>, and the VR4300 will then just isolate the requested 8 bits.

* Writes: VR4300 puts the address on the bus, the size of the access, and then the 32-bit value to be written. When the access is made using 8 or 16 bits, the value on the bus is prepared to match with the aligned 32-bit address. This is the same of what happens for reads, but this time it is the VR4300 tothat prepareprepares the data. For instance, if register <code>S0=0x1234'5678</code>, <code>A0=0x00000x0400'0001</code> and the opcode <code>SB S0, 0(A0)</code> is run, the VR4300 puts on the bus the value <code>S0 << 248</code>, that is <code>0x56780x3456'00007800</code>. ItRCP isignores thenthe uplower to2 bits of the RCPaddress toand seethe that'''access size''', sinceso theany addressRCP isregister or Mapped memory will treat it as 32bit write of <code>0x00000x3456'00017800</code>, it needs to isolate the the second byte <code>0x78Address & 0xfffffffc</code>., So even if it's is aan 8- bit write opcode, otherthe upper bits of the register <code>S0</code> "leak" ononto the bus. However, the lower bits of '''address''' and '''access size''' are passed on to the RDRAM devices (see below).

=== Range 0x0000'0000 - 0x007F0x03EF'FFFF (RDRAM memory) ===

The accesses in this area are handled by RCP via RI (Ram Interface). When the VR4300 reads or writes a location in this range, it gets stalled while the RI communicates with the RDRAM via the RAMBUS serial protocol. As soon as the read or write is finished, the VR4300 is released. Effectively, all reads and writes are synchronous (blocking) from the point of view of the VR4300, as you would expect when accessing a RAM. All access sizes work correctly: 8-bit, 16-bit, 32-bit, 64-bit. Support smaller access sizes is implemented the RDRAM device, which uses the lower bits of '''address''' and '''access size''' passed from RCP to generate a byte mask.

=== Range 0x1FC0'0000 - 0x1FCF'FFFF (PIFSI accessexternal via SIbus) ===

Accesses in this area are affected by the same simplified SysAD implementation described above, so '''access size is ignored.''' Only uncached accesses are allowed; cached accesses will be ignored by RCP causing a VR4300 freeze, requiring a hard reboot. The effect is the same described before.

* All writes are performed '''asynchronously''' by the PI. Making a write in this area will in fact just cause the PI to latch the value internally, and release the VR4300 immediately. The write will then happen in background. The status of the ongoing write will be reflected by the PI "I/O busy" status bit, which will be set to 1 until the write is finalized. While a write is ongoing, further writes are ignored, and reads (from any address) return the 32-bit value that is being written. For further information on this, please check the [[Peripheral Interface|PI page]]. Notice that the PI doesn't know whether a certain device is read-only, so even writes in the ROM area follow this pattern; they are just ignored by the ROM itself.

* AllThe external accessesPI arebus made by RCP through ais 16-bit bus. Given that the RCP only knows of 32-bit accesses (as access size is ignored), this means that each read or write performed by the VR4300 will cause exactly two reads or two writes on the 16-bitPI bus: first the MSB at the address specified by the CPU (ignoring bit 0, so that the address is aligned to 16 bit), then the LSB at address+2. This might seem a small implementation detail, but it does actually cause an important and visible bug. For instance, if the VR4300 requests a 16-bit read at address <code>0x1000'0002</code>, the RCP (that ignores access sizes) will do two 16-bit reads on the cartridge bus at <code>0x1000'0002</code> and <code>0x1000'0004</code>, and will put on the SysAD bus the 32-bit word at <code>0x1000'0002 - 0x1000'0005</code>. This is a violation of the SysAD protocol explained above: in fact, in reply to a 16-bit read at <code>0x1000'0002</code>, the RCP should have put on the bus the 32-bit word at <code>0x1000'0000 - 0x1000'0003</code> instead. Because of this, effectively a 16-bit read at <code>0x1000'0002</code> returns the 16-bit word at <code>0x1000'0004</code> instead.