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MIPS Interface (view source)

Revision as of 01:46, 28 March 2024

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MI_BB_INTERRUPT and MI_BB_MASK
VisualWikitext
(MI_BB_RANDOM register)
(MI_BB_INTERRUPT and MI_BB_MASK)
Line 200:
==== <span style="display:none;">0x0430 000C - MI_MASK</code> ====
----
{{#invoke:Register table|head|550px650px|MI_MASK <code>0x0430 000C</code> (Read)}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| U-0 || U-0 || R-0 || R-0 || R-0 || R-0 || R-0 || R-0
|-
| — || — || DP || PI || VI || AI || SI || SP
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 5 | DP | DP Interrupt Mask
| 4 | PI | PI Interrupt Mask
| 3 | VI | VI Interrupt Mask
| 2 | AI | AI Interrupt Mask
| 1 | SI | SI Interrupt Mask
| 0 | SP | SP Interrupt Mask
}}
 
{{#invoke:Register table|head|650px|MI_MASK <code>0x0430 000C</code> (Write)}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
Line 212 ⟶ 239:
| U-0 || U-0 || U-0 || U-0 || W-0 || W-0 || W-0 || W-0
|-
| — || — || — || — || colspan="4"Set DP || Clear DP || Set PI || DetailsClear BelowPI
{{#invoke:Register table|row|7:0}}
| W-0 || W-0 || RWW-0 || RWW-0 || RWW-0 || UW-0 || RWW-0 || RWW-0
|-
| Set VI || Clear VI || Set AI || Clear AI || Set SI || Clear SI || Set SP || Clear SP
| colspan="8" | Details Below
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
<pre>
| 11 | Set DP | Set DP Interrupt Mask
READ: WRITE:
| 10 | Clear [11]DP | — [11] SetClear DP Interrupt Mask
| 9 | Set [10]PI | Set — [10] Clear DPPI Interrupt Mask
| 8 | Clear [9]PI | — [9] SetClear PI Interrupt Mask
| 7 | Set [8]VI | Set — [8] Clear PIVI Interrupt Mask
| 6 | Clear [7]VI | — [7] SetClear VI Interrupt Mask
| 5 | Set [6]AI | Set — [6] Clear VIAI Interrupt Mask
| 4 | Clear [5]AI | DP Interrupt Mask [5] SetClear AI Interrupt Mask
| 3 | Set [4]SI | Set PI Interrupt Mask [4] Clear AISI Interrupt Mask
| 2 | Clear [3]SI | VI Interrupt Mask [3] SetClear SI Interrupt Mask
| 1 | Set [2]SP | Set AI Interrupt Mask [2] Clear SISP Interrupt Mask
| 0 | Clear [1]SP | SI Interrupt Mask [1] SetClear SP Interrupt Mask
}}
[0] SP Interrupt Mask [0] Clear SP Interrupt Mask
 
</pre>Notice that disabling an interrupt does not prevent the interrupt to be raised in MI_INTERRUPT. It just prevents the interrupt to be signaled to the CPU. If a mask is enabled while the respective interrupt is already set in MI_INTERRUPT, the interrupt is signaled to the CPU right away.
'''Extra Details:'''
 
Notice that disabling an interrupt does not prevent the interrupt to be raised in MI_INTERRUPT. It just prevents the interrupt to be signaled to the CPU. If a mask is enabled while the respective interrupt is already set in MI_INTERRUPT, the interrupt is signaled to the CPU right away.
 
= iQue Player-specific registers =
Line 302 ⟶ 332:
| 0 | Random | Single bit hardware-generated random value. Accumulating bits from this register can produce larger random numbers that are (theoretically) suitable for cryptographic purposes. The Secure Kernel uses this for gathering entropy as part of generating new cryptographic keys.
}}
 
==== <span style="display:none;">0x0430 0038 - MI_BB_INTERRUPT</code> ====
----
{{#invoke:Register table|head|800px|MI_BB_INTERRUPT <code>0x0430 0038</code>}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || R-0 || R-0
|-
| — || — || — || — || — || — || MD_STATE || BTN_STATE
{{#invoke:Register table|row|23:16}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || RW-0 || R-0 || R-0 || R-0 || R-0 || R-0
|-
| — || — || MD || BTN || USB1 || USB0 || PI_ERR || IDE
{{#invoke:Register table|row|7:0}}
| R-0 || R-0 || R-0 || R-0 || R-0 || R-0 || R-0 || R-0
|-
| AES || FLASH || DP || PI || VI || AI || SI || SP
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 15 | MD_STATE | If 0, indicates that the memory card is present. If 1, indicates that the memory card is currently removed.
| 14 | BTN_STATE | If 0, indicates that the power button is not currently held. If 1, indicates that the power button is currently held.
| 13 | MD | Interrupt flag - Set when the memory card is removed from the console. Writing to this bit clears the interrupt.
| 12 | BTN | Interrupt flag - Set when the power button is pressed
| 11 | USB1 | Interrupt flag - Set by USB events on connector 1 (TOVERIFY what kind of events?)
| 10 | USB0 | Interrupt flag - Set by USB events on connector 0 (TOVERIFY what kind of events?)
| 9 | PI_ERR | Interrupt flag - Set on "PI Errors"? (TOVERIFY what sort of errors?)
| 8 | IDE | Interrupt flag - IDE (TODO What is IDE? Only the name is known from some library debug info)
| 7 | AES | Interrupt flag - Set when an AES decryption operation completes
| 6 | FLASH | Interrupt flag - Set when a NAND command completes
| 5 | DP | Interrupt flag - Same as N64 (see MI_INTERRUPT)
| 4 | PI | Interrupt flag - Same as N64 (see MI_INTERRUPT)
| 3 | VI | Interrupt flag - Same as N64 (see MI_INTERRUPT)
| 2 | AI | Interrupt flag - Same as N64 (see MI_INTERRUPT)
| 1 | SI | Interrupt flag - Same as N64 (see MI_INTERRUPT)
| 0 | SP | Interrupt flag - Same as N64 (see MI_INTERRUPT)
}}
 
'''Extra Details:'''
 
The additional iQue-specific interrupts in bits 6 through 13 raise Int1 in the COP0 Cause register rather than Int0 like the N64's RCP interrupts. On N64 Int1 was attached to the Cartridge and Disk Drive ports.
 
==== <span style="display:none;">0x0430 003C - MI_BB_MASK</code> ====
----
{{#invoke:Register table|head|650px|MI_BB_MASK <code>0x0430 003C</code> (Read)}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || R-0 || R-0 || R-0 || R-0|| R-0 || R-0
|-
| — || — || MD || BTN || USB1 || USB0 || PI_ERR || IDE
{{#invoke:Register table|row|7:0}}
| R-0 || R-0 || R-0 || R-0 || R-0 || R-0 || R-0 || R-0
|-
| AES || FLASH || DP || PI || VI || AI || SI || SP
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 13 | MD | MD Interrupt Mask
| 12 | BTN | BTN Interrupt Mask
| 11 | USB1 | USB1 Interrupt Mask
| 10 | USB0 | USB0 Interrupt Mask
| 9 | PI_ERR | PI_ERR Interrupt Mask
| 8 | IDE | IDE Interrupt Mask
| 7 | AES | AES Interrupt Mask
| 6 | FLASH | FLASH Interrupt Mask
| 5 | DP | DP Interrupt Mask
| 4 | PI | PI Interrupt Mask
| 3 | VI | VI Interrupt Mask
| 2 | AI | AI Interrupt Mask
| 1 | SI | SI Interrupt Mask
| 0 | SP | SP Interrupt Mask
}}
 
{{#invoke:Register table|head|650px|MI_BB_MASK <code>0x0430 003C</code> (Write)}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || W-0 || W-0 || W-0 || W-0
|-
| — || — || — || — || Set MD || Clear MD || Set BTN || Clear BTN
{{#invoke:Register table|row|23:16}}
| W-0 || W-0 || W-0 || W-0 || W-0 || W-0 || W-0 || W-0
|-
| Set USB1 || Clear USB1 || Set USB0 || Clear USB0 || Set PI_ERR || Clear PI_ERR || Set IDE || Clear IDE
{{#invoke:Register table|row|15:8}}
| W-0 || W-0 || W-0 || W-0 || W-0 || W-0 || W-0 || W-0
|-
| Set AES || Clear AES || Set FLASH || Clear FLASH || Set DP || Clear DP || Set PI || Clear PI
{{#invoke:Register table|row|7:0}}
| W-0 || W-0 || W-0 || W-0 || W-0 || W-0 || W-0 || W-0
|-
| Set VI || Clear VI || Set AI || Clear AI || Set SI || Clear SI || Set SP || Clear SP
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 27 | Set MD | Set MD Interrupt Mask
| 26 | Clear MD | Clear MD Interrupt Mask
| 25 | Set BTN | Set BTN Interrupt Mask
| 24 | Clear BTN | Clear BTN Interrupt Mask
| 23 | Set USB1 | Set USB1 Interrupt Mask
| 22 | Clear USB1 | Clear USB1 Interrupt Mask
| 21 | Set USB0 | Set USB0 Interrupt Mask
| 20 | Clear USB0 | Clear USB0 Interrupt Mask
| 19 | Set PI_ERR | Set PI_ERR Interrupt Mask
| 18 | Clear PI_ERR | Clear PI_ERR Interrupt Mask
| 17 | Set IDE | Set IDE Interrupt Mask
| 16 | Clear IDE | Clear IDE Interrupt Mask
| 15 | Set AES | Set AES Interrupt Mask
| 14 | Clear AES | Clear AES Interrupt Mask
| 13 | Set FLASH | Set FLASH Interrupt Mask
| 12 | Clear FLASH | Clear FLASH Interrupt Mask
| 11 | Set DP | Set DP Interrupt Mask
| 10 | Clear DP | Clear DP Interrupt Mask
| 9 | Set PI | Set PI Interrupt Mask
| 8 | Clear PI | Clear PI Interrupt Mask
| 7 | Set VI | Set VI Interrupt Mask
| 6 | Clear VI | Clear VI Interrupt Mask
| 5 | Set AI | Set AI Interrupt Mask
| 4 | Clear AI | Clear AI Interrupt Mask
| 3 | Set SI | Set SI Interrupt Mask
| 2 | Clear SI | Clear SI Interrupt Mask
| 1 | Set SP | Set SP Interrupt Mask
| 0 | Clear SP | Clear SP Interrupt Mask
}}
 
'''Extra Details:'''
 
Notice that disabling an interrupt does not prevent the interrupt to be raised in MI_BB_INTERRUPT. It just prevents the interrupt to be signaled to the CPU. If a mask is enabled while the respective interrupt is already set in MI_BB_INTERRUPT, the interrupt is signaled to the CPU right away.
 
The interrupts shared with N64 are mirrors of the MI_MASK state. Updating one register updates the other automatically.
Tharo
56

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