MIPS Interface: Difference between revisions
MI_BB_RANDOM register
(Few more details for MI_BB_SECURE_EXCEPTION) |
(MI_BB_RANDOM register) |
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: Secure traps are implemented as an NMI to the CPU and are vectored to 0xBFC00000, this register is then used by the Secure Kernel as a Cause register to determine the reason for the secure trap and the relevant handler is entered.
: Reading (and possibly writing, TOVERIFY) this register from non-secure mode (i.e. from a game or application) causes a secure trap with the Application bit set in this register. This mechanism is how SKCs (Secure Kernel calls) are implemented; the application sets up the required CPU registers for the call before reading this register to trigger the Application trap.
==== <span style="display:none;">0x0430 002C - MI_BB_RANDOM</code> ====
----
{{#invoke:Register table|head|700px|MI_BB_RANDOM <code>0x0430 002C</code>}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || R-?
|-
| — || — || — || — || — || — || — || Random
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 0 | Random | Single bit hardware-generated random value. Accumulating bits from this register can produce larger random numbers that are (theoretically) suitable for cryptographic purposes. The Secure Kernel uses this for gathering entropy as part of generating new cryptographic keys.
}}
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