MIPS Interface: Difference between revisions
Few more details for MI_BB_SECURE_EXCEPTION
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(Few more details for MI_BB_SECURE_EXCEPTION) |
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==== <span style="display:none;">0x0430 0014 - MI_BB_SECURE_EXCEPTION</code> ====
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{{#invoke:Register table|head|
{{#invoke:Register table|row|31:24}}
| U-? || U-? || U-? || U-? || U-? || U-? ||
|-
| — || — || — || — || — || — || — ||
{{#invoke:Register table|row|23:16}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
Line 254:
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? ||
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| RW-
|-
|
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 25 | Unknown | System software writes to this bit when launching an app or game. (TODO determine the purpose of this bit)
| 6 | Button | Secure trap caused by the power button being pressed▼
| 24 | SK RAM Access | Setting this bit to 1 enables access to an 0x8000-byte SRAM mapped at 0x1FC40000 outside of secure mode.
| 5 | MI error | Secure trap caused by an MI error▼
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|
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| 2 | Application | Secure trap caused by an application reading this register outside of secure mode.
| 1 | Boot memory swap | If this is set to 1 the boot ROM is mapped to 0x1FC00000 and Secure Kernel RAM is mapped at 0x1FC20000; this is the state at cold boot. If this is not set the Secure Kernel RAM is mapped at 0x1FC00000 and the boot ROM is mapped at 0x1FC20000.
| 0 | Secure mode | Secure Kernel writes 0 here to exit secure mode. This is effective immediately, all future memory accesses that miss the CPU cache will be unable to access secure mode resources. Whenever this register is written to without the intention to exit secure mode, a 1 must be re-written here.
}}
'''Extra Details:'''
: Secure traps are implemented as an NMI to the CPU and are vectored to 0xBFC00000, this register is then used by the Secure Kernel as a Cause register to determine the reason for the secure trap and the relevant handler is entered.
: Reading (and possibly writing, TOVERIFY) this register from non-secure mode
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