MIPS Interface: Difference between revisions
Document MI_BB_SECURE_EXCEPTION to test iQue Player register documentation layout
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Accesses beyond <code>0x0430 0010</code> are mirrored, so only the least significant four bits are taken into account for address decoding.
(Note that this isn't the case on the iQue Player.)
= Registers =
Line 231 ⟶ 233:
[0] SP Interrupt Mask [0] Clear SP Interrupt Mask
</pre>Notice that disabling an interrupt does not prevent the interrupt to be raised in MI_INTERRUPT. It just prevents the interrupt to be signaled to the CPU. If a mask is enabled while the respective interrupt is already set in MI_INTERRUPT, the interrupt is signaled to the CPU right away.
= iQue Player-specific registers =
'''Table Notation:'''
<pre>
R = Readable bit
W = Writable bit
U = Undefined/Unused bit
-n = Default value n at power on
[x:y] = Specifies bits x to y, inclusively</pre>
==== <span style="display:none;">0x0430 0014 - MI_BB_SECURE_EXCEPTION</code> ====
----
{{#invoke:Register table|head|550px|MI_BB_SECURE_EXCEPTION <code>0x0430 0014</code>}}
{{#invoke:Register table|row|31:24}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || RW-?
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
|-
| — || Button || MI error || PI error || Timer || App. || — || Secure mode
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 6 | Button | Secure trap caused by the power button being pressed
| 5 | MI error | Secure trap caused by an MI error
| 4 | PI error | Secure trap caused by a PI error
| 3 | Timer | Secure trap caused by the secure timer
| 2 | Application | Secure trap caused by an application calling an SKC (see below)
| 0 | Secure mode | SK writes 0 here to exit secure mode; the bootrom writes 1 here just before jumping to SK, but it's not known what effect this has.
}}
'''Extra Details:'''
: The bootrom writes 0 to bit 1 just before jumping to SK; it's also unknown what effect this has.
: Reading this register from non-secure mode, i.e. as a game or application, causes a secure trap (execution jumps to the beginning of the secure kernel and the console enters secure mode) with the Application bit set in the register. Presumably, writing the register has the same effect, but this hasn't been checked.
: This mechanism is how SKCs (secure kernel calls) are implemented; the application sets up the required CPU registers for the call, then reads from `MI_BB_SECURE_EXCEPTION` to trigger the trap.
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