MIPS Interface: Difference between revisions
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→0x0430 0000 - MI_MODE: fix copypasta
(Fix order of Set/Clear) |
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Line 66:
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 13 | SetUpper | Set
| 12 | ClearUpper |
| 11 | ClearDP | Clear the DP Interrupt.
| 10 | SetEBus | Set Ebus mode.
Line 92:
: '''Repeat Mode:''' 32bit writes result in <code>RepeatCount + 1</code> bytes being written, with the same 32bit word repeating every 32bits. Reading with this mode can cause a hang. <br>In this mode, MI duplicates the 32bit word into both the upper and lower half of DBUS, and then lies to RI about the transfer count. Instead of 4, it sends ```RepeatCount```. The full Count is inserted into the Rambus request packet and the Rambus device uses the lower 3 bits for byte masking. RI looks at RepeatCount[6:3] to calculate the number 64bit transfers.
: This mode is labeled as '''"Init Mode"''' in some documentation. It's only used once during IPL3's RDRAM initialization to do a broadcast write to the '''Delay''' register. This is needed because after reset, the default timings in the '''Delay''' register result in the Rambus device sampling the data from the Rambus way too late and sampling garbage data. RI's timings are baked into hardware and can't be changed, but IPL3 uses a clever trick:<Br>
By enabling Repeat Mode and setting RepeatCount to 15, the 32bit value is repeated 4 times, and the Rambus device now samples valid data into the '''Delay''' register. However, the default timings aren't off by an integer multiple of the RCP clock, and the Rambus device samples halfway between two repetitions of the 32bit word. To work around this, IPL3 rotates the value by 16 bits before writing.
==== <span style="display:none;">0x0430 0004 - MI_VERSION</code> ====
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