MIPS Interface: Difference between revisions
→0x0430 0008 - MI_INTERRUPT
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{{#invoke:Register table|definitions
| 31-6 | Undefined | Initialized to <code>0</code>
| 5 | DP | Interrupt flag - Set when the RDP finishes a full sync
| 4 | PI | Interrupt flag - Set when a PI DMA transfer finishes
| 3 | VI | Interrupt flag - Set when the VI starts processing a specific half-line of the screen (<code>VI_V_CURRENT {{=}}{{=}} VI_V_INTR</code>). Usually, this is configured with `VI_V_CURRENT = 2` so that it behaves as a VBlank interrupt.
| 2 | AI | Interrupt flag - Set when
| 1 | SI | Interrupt flag - Set when a SI DMA to/from PIF RAM finishes
| 0 | SP | Interrupt flag - Set when the RSP executes a BREAK opcode while SP_STATUS has been configured with the INTERRUPT_ON_BRAK bit; alternatively, it can also be set by explicitly writing the `INTERRUPT` flag in the SP_STATUS register (by either the CPU or the RSP itself).
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==== <span style="display:none;">0x0430 000C - MI_MASK</code> ====
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