MIPS Interface: Difference between revisions
Added bit details for MI_INTERRUPT
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(Added bit details for MI_INTERRUPT) |
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Line 94:
{{#invoke:Register table|definitions
| 31-6 | Undefined | Initialized to <code>0</code>
| 5 | DP | Interrupt flag - Set when a full sync completes
| 4 | PI | Interrupt flag - Set when a PI DMA finishes
| 3 | VI | Interrupt flag - Set when <code>VI_V_CURRENT {{=}}{{=}} VI_V_INTR</code>
| 2 | AI | Interrupt flag - Set when no more samples remain in an audio stream
| 1 | SI | Interrupt flag - Set when a SI DMA to/from PIF RAM finishes
| 0 | SP | Interrupt flag
}}
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