MIPS Interface: Difference between revisions

Fix order of Set/Clear
(Minor formatting fixes)
(Fix order of Set/Clear)
Line 59:
| U-0 || U-0 || W-0 || W-0 || W-0 || W-0 || RW-0 || RW-0
|-
| — || — || Set Upper || Clear Upper || ClearDP || ClearSet Ebus || SetClear Ebus || ClearSet Repeat
{{#invoke:Register table|row|7:0}}
| W-0 || RW-0 || RW-0 || RW-0 || RW-0 || U-0 || RW-0 || RW-0
|-
| SetClear Repeat || colspan="7" | RepeatCount[6:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 13 | SetUpper | Set Ebus mode.
| 12 | ClearUpper | Set Ebus mode.
| 11 | ClearDP | Clear the DP interruptInterrupt.
| 10 | ClearEBusSetEBus | ClearSet Ebus mode.
| 9 | SetEBusClearEBus | SetClear Ebus mode.
| 8 | ClearRepeatSetRepeat | ClearSet repeat mode. Automatically clears after a single write.
| 7 | SetRepeatClearRepeat | SetClear repeat mode. Automatically clears after a single write.
| 6-0 | RepeatCount[6:0] | Number of bytes (minus 1) to write in repeat mode
}}
22

edits