MIPS Interface: Difference between revisions
MI_BB_SECURE_EXCEPTION: Add a link to the SKCs page
(MI_BB_INTERRUPT and MI_BB_MASK) |
(MI_BB_SECURE_EXCEPTION: Add a link to the SKCs page) |
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'''Extra Details:'''
: Secure traps are implemented as an NMI to the CPU and are vectored to 0xBFC00000, this register is then used by the Secure Kernel as a Cause register to determine the reason for the secure trap and the relevant handler is entered.
: Reading (and possibly writing, TOVERIFY) this register from non-secure mode (i.e. from a game or application) causes a secure trap with the Application bit set in this register. This mechanism is how SKCs ([[Secure Kernel
==== <span style="display:none;">0x0430 002C - MI_BB_RANDOM</code> ====
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