MIPS Interface: Difference between revisions
MI_BB_INTERRUPT and MI_BB_MASK
(Rewrite RepeatMode with better examples) |
(MI_BB_INTERRUPT and MI_BB_MASK) |
||
| (7 intermediate revisions by 4 users not shown) | |||
Line 3:
Memory mapped registers are used to configure the MIPS Interface. The base address for these registers is <code>0x0430 0000</code>, also known as MI_BASE. However, because all memory accesses in the CPU are made using virtual addresses, the following addresses must be offset appropriately. For non-cached reads/writes, add <code>0xA000 0000</code> to the address. As an example, to directly write to the MI_MODE register, use address <code>0xA430 0000</code>.
Note that some of these registers have different behavior when writing to them, than when reading from them. When writing to a register that has Set and Clear bits, write a 1 on the desired bit. Writing 0's have no effect.
Accesses beyond <code>0x0430 0010</code> are mirrored, so only the
(Note that this isn't the case on the iQue Player.)
= Registers =
Line 88 ⟶ 90:
: '''Upper mode:''' 32bit transfers are always shifted into the upper half of the 64bit bus.<Br> This mode is labeled as '''"RDRAM register mode"''' in some documentation and is useful for accessing registers on Rambus devices. The Rambus Rreg, Wreg, and WregB commands are hardcoded to ignore the count field of request packets and always do a 32bit transfers. When misinterpreting the RI's 8 byte transfer, the Rambus device always takes the first 4 bytes (which are the upper 32bits of DBus, because RCP is big endian) and ignores the next 4 bytes. Normal mode should produce correct results for registers at even offsets, but you need switch MI into Upper mode to correctly access odd registers.
: '''EBus
: '''Repeat Mode:''' Writes cause a repeating pattern of '''RepeatCount+1''' bytes (upto 128 bytes) to be written. Reading can cause a hang (further testing needed).<br> First a 64bit value is loaded into the DBus FIFO to be the pattern:
Line 198 ⟶ 200:
==== <span style="display:none;">0x0430 000C - MI_MASK</code> ====
----
{{#invoke:Register table|head|
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| U-0 || U-0 || R-0 || R-0 || R-0 || R-0 || R-0 || R-0
|-
| — || — || DP || PI || VI || AI || SI || SP
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 5 | DP | DP Interrupt Mask
| 4 | PI | PI Interrupt Mask
| 3 | VI | VI Interrupt Mask
| 2 | AI | AI Interrupt Mask
| 1 | SI | SI Interrupt Mask
| 0 | SP | SP Interrupt Mask
}}
{{#invoke:Register table|head|650px|MI_MASK <code>0x0430 000C</code> (Write)}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
Line 210 ⟶ 239:
| U-0 || U-0 || U-0 || U-0 || W-0 || W-0 || W-0 || W-0
|-
| — || — || — || — ||
{{#invoke:Register table|row|7:0}}
| W-0 || W-0 ||
|-
| Set VI || Clear VI || Set AI || Clear AI || Set SI || Clear SI || Set SP || Clear SP
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 11 | Set DP | Set DP Interrupt Mask
| 10 | Clear DP | Clear DP Interrupt Mask
| 9 | Set PI | Set PI Interrupt Mask
| 8 | Clear PI | Clear PI Interrupt Mask
| 7 | Set VI | Set VI Interrupt Mask
| 6 | Clear VI | Clear VI Interrupt Mask
| 5 | Set AI | Set AI Interrupt Mask
| 4 | Clear AI | Clear AI Interrupt Mask
| 3 | Set SI | Set SI Interrupt Mask
| 2 | Clear SI | Clear SI Interrupt Mask
| 1 | Set SP | Set SP Interrupt Mask
| 0 | Clear SP | Clear SP Interrupt Mask
}}
'''Extra Details:'''
Notice that disabling an interrupt does not prevent the interrupt to be raised in MI_INTERRUPT. It just prevents the interrupt to be signaled to the CPU. If a mask is enabled while the respective interrupt is already set in MI_INTERRUPT, the interrupt is signaled to the CPU right away.
= iQue Player-specific registers =
'''Table Notation:'''
<pre>
R = Readable bit
W = Writable bit
U = Undefined/Unused bit
-n = Default value n at power on
[x:y] = Specifies bits x to y, inclusively</pre>
==== <span style="display:none;">0x0430 0014 - MI_BB_SECURE_EXCEPTION</code> ====
----
{{#invoke:Register table|head|700px|MI_BB_SECURE_EXCEPTION <code>0x0430 0014</code>}}
{{#invoke:Register table|row|31:24}}
| U-? || U-? || U-? || U-? || U-? || U-? || W-? || W-?
|-
| — || — || — || — || — || — || — || SK RAM Access
{{#invoke:Register table|row|23:16}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-1 || RW-1
|-
| Module || Button || MI error || PI error || Timer || Application || Boot memory swap || Secure mode
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 25 | Unknown | System software writes to this bit when launching an app or game. (TODO determine the purpose of this bit)
| 24 | SK RAM Access | Setting this bit to 1 enables access to an 0x8000-byte SRAM mapped at 0x1FC40000 outside of secure mode.
| 7 | Module | Secure trap caused by the memory card being removed. (TOVERIFY)
| 6 | Button | Secure trap caused by the power button being pressed. (TOVERIFY there should be some way to control whether this event causes a secure trap or an Int2/PreNMI interrupt)
| 5 | MI error | Secure trap caused by an MI error.
| 4 | PI error | Secure trap caused by a PI error.
| 3 | Timer | Secure trap caused by the secure timer.
| 2 | Application | Secure trap caused by an application reading this register outside of secure mode.
| 1 | Boot memory swap | If this is set to 1 the boot ROM is mapped to 0x1FC00000 and Secure Kernel RAM is mapped at 0x1FC20000; this is the state at cold boot. If this is not set the Secure Kernel RAM is mapped at 0x1FC00000 and the boot ROM is mapped at 0x1FC20000.
| 0 | Secure mode | Secure Kernel writes 0 here to exit secure mode. This is effective immediately, all future memory accesses that miss the CPU cache will be unable to access secure mode resources. Whenever this register is written to without the intention to exit secure mode, a 1 must be re-written here.
}}
'''Extra Details:'''
: Secure traps are implemented as an NMI to the CPU and are vectored to 0xBFC00000, this register is then used by the Secure Kernel as a Cause register to determine the reason for the secure trap and the relevant handler is entered.
: Reading (and possibly writing, TOVERIFY) this register from non-secure mode (i.e. from a game or application) causes a secure trap with the Application bit set in this register. This mechanism is how SKCs (Secure Kernel calls) are implemented; the application sets up the required CPU registers for the call before reading this register to trigger the Application trap.
==== <span style="display:none;">0x0430 002C - MI_BB_RANDOM</code> ====
----
{{#invoke:Register table|head|700px|MI_BB_RANDOM <code>0x0430 002C</code>}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || R-?
|-
| — || — || — || — || — || — || — || Random
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 0 | Random | Single bit hardware-generated random value. Accumulating bits from this register can produce larger random numbers that are (theoretically) suitable for cryptographic purposes. The Secure Kernel uses this for gathering entropy as part of generating new cryptographic keys.
}}
==== <span style="display:none;">0x0430 0038 - MI_BB_INTERRUPT</code> ====
----
{{#invoke:Register table|head|800px|MI_BB_INTERRUPT <code>0x0430 0038</code>}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || R-0 || R-0
|-
| — || — || — || — || — || — || MD_STATE || BTN_STATE
{{#invoke:Register table|row|23:16}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || RW-0 || R-0 || R-0 || R-0 || R-0 || R-0
|-
| — || — || MD || BTN || USB1 || USB0 || PI_ERR || IDE
{{#invoke:Register table|row|7:0}}
| R-0 || R-0 || R-0 || R-0 || R-0 || R-0 || R-0 || R-0
|-
| AES || FLASH || DP || PI || VI || AI || SI || SP
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 15 | MD_STATE | If 0, indicates that the memory card is present. If 1, indicates that the memory card is currently removed.
| 14 | BTN_STATE | If 0, indicates that the power button is not currently held. If 1, indicates that the power button is currently held.
| 13 | MD | Interrupt flag - Set when the memory card is removed from the console. Writing to this bit clears the interrupt.
| 12 | BTN | Interrupt flag - Set when the power button is pressed
| 11 | USB1 | Interrupt flag - Set by USB events on connector 1 (TOVERIFY what kind of events?)
| 10 | USB0 | Interrupt flag - Set by USB events on connector 0 (TOVERIFY what kind of events?)
| 9 | PI_ERR | Interrupt flag - Set on "PI Errors"? (TOVERIFY what sort of errors?)
| 8 | IDE | Interrupt flag - IDE (TODO What is IDE? Only the name is known from some library debug info)
| 7 | AES | Interrupt flag - Set when an AES decryption operation completes
| 6 | FLASH | Interrupt flag - Set when a NAND command completes
| 5 | DP | Interrupt flag - Same as N64 (see MI_INTERRUPT)
| 4 | PI | Interrupt flag - Same as N64 (see MI_INTERRUPT)
| 3 | VI | Interrupt flag - Same as N64 (see MI_INTERRUPT)
| 2 | AI | Interrupt flag - Same as N64 (see MI_INTERRUPT)
| 1 | SI | Interrupt flag - Same as N64 (see MI_INTERRUPT)
| 0 | SP | Interrupt flag - Same as N64 (see MI_INTERRUPT)
}}
'''Extra Details:'''
The additional iQue-specific interrupts in bits 6 through 13 raise Int1 in the COP0 Cause register rather than Int0 like the N64's RCP interrupts. On N64 Int1 was attached to the Cartridge and Disk Drive ports.
==== <span style="display:none;">0x0430 003C - MI_BB_MASK</code> ====
----
{{#invoke:Register table|head|650px|MI_BB_MASK <code>0x0430 003C</code> (Read)}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || R-0 || R-0 || R-0 || R-0|| R-0 || R-0
|-
| — || — || MD || BTN || USB1 || USB0 || PI_ERR || IDE
{{#invoke:Register table|row|7:0}}
| R-0 || R-0 || R-0 || R-0 || R-0 || R-0 || R-0 || R-0
|-
| AES || FLASH || DP || PI || VI || AI || SI || SP
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 13 | MD | MD Interrupt Mask
| 12 | BTN | BTN Interrupt Mask
| 11 | USB1 | USB1 Interrupt Mask
| 10 | USB0 | USB0 Interrupt Mask
| 9 | PI_ERR | PI_ERR Interrupt Mask
| 8 | IDE | IDE Interrupt Mask
| 7 | AES | AES Interrupt Mask
| 6 | FLASH | FLASH Interrupt Mask
| 5 | DP | DP Interrupt Mask
| 4 | PI | PI Interrupt Mask
| 3 | VI | VI Interrupt Mask
| 2 | AI | AI Interrupt Mask
| 1 | SI | SI Interrupt Mask
| 0 | SP | SP Interrupt Mask
}}
{{#invoke:Register table|head|650px|MI_BB_MASK <code>0x0430 003C</code> (Write)}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || W-0 || W-0 || W-0 || W-0
|-
| — || — || — || — || Set MD || Clear MD || Set BTN || Clear BTN
{{#invoke:Register table|row|23:16}}
| W-0 || W-0 || W-0 || W-0 || W-0 || W-0 || W-0 || W-0
|-
| Set USB1 || Clear USB1 || Set USB0 || Clear USB0 || Set PI_ERR || Clear PI_ERR || Set IDE || Clear IDE
{{#invoke:Register table|row|15:8}}
| W-0 || W-0 || W-0 || W-0 || W-0 || W-0 || W-0 || W-0
|-
| Set AES || Clear AES || Set FLASH || Clear FLASH || Set DP || Clear DP || Set PI || Clear PI
{{#invoke:Register table|row|7:0}}
| W-0 || W-0 || W-0 || W-0 || W-0 || W-0 || W-0 || W-0
|-
| Set VI || Clear VI || Set AI || Clear AI || Set SI || Clear SI || Set SP || Clear SP
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 27 | Set MD | Set MD Interrupt Mask
| 26 | Clear MD | Clear MD Interrupt Mask
| 25 | Set BTN | Set BTN Interrupt Mask
| 24 | Clear BTN | Clear BTN Interrupt Mask
| 23 | Set USB1 | Set USB1 Interrupt Mask
| 22 | Clear USB1 | Clear USB1 Interrupt Mask
| 21 | Set USB0 | Set USB0 Interrupt Mask
| 20 | Clear USB0 | Clear USB0 Interrupt Mask
| 19 | Set PI_ERR | Set PI_ERR Interrupt Mask
| 18 | Clear PI_ERR | Clear PI_ERR Interrupt Mask
| 17 | Set IDE | Set IDE Interrupt Mask
| 16 | Clear IDE | Clear IDE Interrupt Mask
| 15 | Set AES | Set AES Interrupt Mask
| 14 | Clear AES | Clear AES Interrupt Mask
| 13 | Set FLASH | Set FLASH Interrupt Mask
| 12 | Clear FLASH | Clear FLASH Interrupt Mask
| 11 | Set DP | Set DP Interrupt Mask
| 10 | Clear DP | Clear DP Interrupt Mask
| 9 | Set PI | Set PI Interrupt Mask
| 8 | Clear PI | Clear PI Interrupt Mask
| 7 | Set VI | Set VI Interrupt Mask
| 6 | Clear VI | Clear VI Interrupt Mask
| 5 | Set AI | Set AI Interrupt Mask
| 4 | Clear AI | Clear AI Interrupt Mask
| 3 | Set SI | Set SI Interrupt Mask
| 2 | Clear SI | Clear SI Interrupt Mask
| 1 | Set SP | Set SP Interrupt Mask
| 0 | Clear SP | Clear SP Interrupt Mask
}}
'''Extra Details:'''
Notice that disabling an interrupt does not prevent the interrupt to be raised in MI_BB_INTERRUPT. It just prevents the interrupt to be signaled to the CPU. If a mask is enabled while the respective interrupt is already set in MI_BB_INTERRUPT, the interrupt is signaled to the CPU right away.
The interrupts shared with N64 are mirrors of the MI_MASK state. Updating one register updates the other automatically.
| |||