FAQ: Difference between revisions

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'''Short answer:''' 4 GiB, without bank switchers. Unlimited otherwise.

Most people seem to believe that Nintendo 64 is somehow limited to cartridge of 64 MiB. The origin of this belief is likely the fact that 64 MiB is the maximum size used by retail games (such as Conker: Bad Fur Day). In fact, there is no such a hardware limit. The cartridge is accessed via the [[PI|PI bus]], a serial bus that allows for full 32-bit addresses, accessible via DMA: so a hardware cartridge can reply with data to any address in the 32-bit range. ROMs must have a valid header at address <code>1000'0000</code>, but besides that, there is absolutely no constraint: a cartridge could also reply with data in the range <code>0000'0000</code> - <code>0FFF'FFFF</code>, as long as the application itself knows about it and retrieves it when necessary.

Most people seem to believe that Nintendo 64 is somehow limited to cartridge of 64 MiB. The origin of this belief is likely the fact that 64 MiB is the maximum size used by retail games (such as Conker: Bad Fur Day). In fact, there is no such a hardware limit. The cartridge is accessed via the [[PI|PI bus]], a serial bus that allows for full 32-bit addresses, accessible via DMA: so a hardware cartridge can reply with data to any address in the 32-bit range, that is a total of 4 GiB. ROMs must have a valid header at address <code>1000'0000</code>, but besides that, there is absolutely no constraint: a cartridge could also reply with data in the range <code>0000'0000</code> - <code>0FFF'FFFF</code>, as long as the application itself knows about it and retrieves it when necessary.

~~Some~~ of the address space is also [[Memory map|memory-mapped]] to the VR4300 (and that includes normally the whole ROM too), but that is not a limit or a constraint in any way. It is true that ~~the~~ full 32-bit address space is accessible only via DMA, but that is actually the main (and almost only) way a ROM is normally accessed: direct I/O accesses via CPUs in memory mapped areas are rather slow, cannot be cached, and only work correctly with 32-bit access size. So in practice they are rarely used.

Others seem to believe the maximum size is 252 MiB. That belief comes from the fact that some of the address space of the PI bus is also [[Memory map|memory-mapped]] to the VR4300 (and that includes normally the whole ROM too), and in fact 252 MiB of it is memory mapped in the physical range <code>0x10000000-0x1FBFFFFF</code> but that is not a limit or a constraint in any way. There is no technical constraints preventing a cartridge to expose a larger area to the PI bus (up to 4 GiB). It is true that this full 32-bit address space is accessible only via DMA, but that is actually the main (and almost only) way a ROM is normally accessed: direct I/O accesses via CPUs in memory mapped areas are rather slow, cannot be cached, and only work correctly with 32-bit access size. So in practice they are rarely used.

At the hardware level, the presence of a serial bus means that it is possible to split ROM contents across a different array of chips if required; as long as the PI bus decoding logic knows how to map each address to the correct chip, it will be fine.

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 '''Short answer:''' 4 GiB, without bank switchers. Unlimited otherwise.
-Most people seem to believe that Nintendo 64 is somehow limited to cartridge of 64 MiB. The origin of this belief is likely the fact that 64 MiB is the maximum size used by retail games (such as Conker: Bad Fur Day). In fact, there is no such a hardware limit. The cartridge is accessed via the [[PI|PI bus]], a serial bus that allows for full 32-bit addresses, accessible via DMA: so a hardware cartridge can reply with data to any address in the 32-bit range. ROMs must have a valid header at address <code>1000'0000</code>, but besides that, there is absolutely no constraint: a cartridge could also reply with data in the range <code>0000'0000</code> - <code>0FFF'FFFF</code>, as long as the application itself knows about it and retrieves it when necessary.
+Most people seem to believe that Nintendo 64 is somehow limited to cartridge of 64 MiB. The origin of this belief is likely the fact that 64 MiB is the maximum size used by retail games (such as Conker: Bad Fur Day). In fact, there is no such a hardware limit. The cartridge is accessed via the [[PI|PI bus]], a serial bus that allows for full 32-bit addresses, accessible via DMA: so a hardware cartridge can reply with data to any address in the 32-bit range, that is a total of 4 GiB. ROMs must have a valid header at address <code>1000'0000</code>, but besides that, there is absolutely no constraint: a cartridge could also reply with data in the range <code>0000'0000</code> - <code>0FFF'FFFF</code>, as long as the application itself knows about it and retrieves it when necessary.
-Some of the address space is also [[Memory map|memory-mapped]] to the VR4300 (and that includes normally the whole ROM too), but that is not a limit or a constraint in any way. It is true that the full 32-bit address space is accessible only via DMA, but that is actually the main (and almost only) way a ROM is normally accessed: direct I/O accesses via CPUs in memory mapped areas are rather slow, cannot be cached, and only work correctly with 32-bit access size. So in practice they are rarely used.
+Others seem to believe the maximum size is 252 MiB. That belief comes from the fact that some of the address space of the PI bus is also [[Memory map|memory-mapped]] to the VR4300 (and that includes normally the whole ROM too), and in fact 252 MiB of it is memory mapped in the physical range <code>0x10000000-0x1FBFFFFF</code> but that is not a limit or a constraint in any way. There is no technical constraints preventing a cartridge to expose a larger area to the PI bus (up to 4 GiB).  It is true that this full 32-bit address space is accessible only via DMA, but that is actually the main (and almost only) way a ROM is normally accessed: direct I/O accesses via CPUs in memory mapped areas are rather slow, cannot be cached, and only work correctly with 32-bit access size. So in practice they are rarely used.
 At the hardware level, the presence of a serial bus means that it is possible to split ROM contents across a different array of chips if required; as long as the PI bus decoding logic knows how to map each address to the correct chip, it will be fine.

FAQ: Difference between revisions

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