EverDrive-64 v3: Difference between revisions
→0x08040000 (REG_CFG): RTC
(Reading Data from the Host: clarify that wait for RXF#=0 and DMA is not relevant) |
(→0x08040000 (REG_CFG): RTC) |
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| (8 intermediate revisions by the same user not shown) | |||
Line 41:
| 0x08040018 || REG_SPI || R/W || SPI (SD card) DAT/CMD (write invoke CLK)
|-
| 0x0804001C || REG_SPI_CFG || R/W || SPI (SD card) configurations
|-
| 0x08040020 || REG_KEY || W || Enable or disable ED64 registers
|-
| 0x08040024 || REG_SAV_CFG || R/W || Save configurations (EEPROM/SRAM/FLASH)
|-
| 0x08040028 || REG_SEC || ? || ?
|-
| 0x0804002C || REG_VER || R ||
|-
| 0x08040030 || ? || R/W || I2C to access RTC
Line 59:
| 0x0804003C || ? || ? || ?
|-
| 0x08040040 || REG_CFG_CNT ||
|-
| 0x08040044 || REG_CFG_DAT ||
|-
| 0x08040048 || MAX_MSG || R/W || Some configurations
Line 80:
! bit from lsb !! description
|-
| 15 || 1=
|-
| 9-8 || D64 specific??
|-
| 6-5 ||RTC (00=disable, 01=RTC emulation enabled through Cart EEPROM command 06/07, 11=RTC access enabled via I2C)
|-
| 3 || WR_ADDR_MASK??
Line 198:
=== 0x0804001C (REG_SPI_CFG) ===
Read/Write
{| class="wikitable"
!bit from lsb
Line 231:
=== 0x08040024 (REG_SAV_CFG) ===
Read/Write
{| class="wikitable"
!bit from lsb
Line 237:
|-
|15
|1=enable ED64 save page
|-
|7
|1=enable game save page (have priority than ED64 page)
|-
|3
Line 259:
!description
|-
|0x0080
|Save is disabled
|-
|0x0082
|32KiB SRAM enabled
|-
|0x008A
|128KiB SRAM enabled
|-
|0x0081
|4kibit EEPROM enabled
|-
|0x0085
|16kibit EEPROM enabled
|-
|0x0088
|128KiB Flash enabled (!?)
|-
|0x800A
|128KiB ED64 save page enabled (mainly from 0x1E000)
|}
=== 0x08040028 (REG_SEC) ===
Write only?
=== 0x0804002C (REG_VER) ===
Line 287 ⟶ 290:
|-
|15-8
|
|-
|7-0
|
|}
ex. 0x0304 for
=== 0x08040030 (I2C/RTC) ===
Line 311 ⟶ 314:
=== 0x08040040 (REG_CFG_CNT) ===
Read/Write on REG_CFG&1==0
{| class="wikitable"
!bit from lsb
!description
|-
|3
|1=REG_CFG_DAT is transferring [R]
|-
|2
|1=FPGA is configuring? [R]
|-
|0
|0=unconfigure FPGA? [W]
|}
SDRAM must be disabled (REG_CFG & 1 must be zero).
=== 0x08040044 (REG_CFG_DAT) ===
Write only? on REG_CFG&1==0
{| class="wikitable"
!bit from lsb
!description
|-
|15-0
|configuration data (part of bitstream)
|}
SDRAM must be disabled (REG_CFG & 1 must be zero).
=== 0x08040048 (REG_MAX_MSG) ===
Read/Write on REG_CFG&1==0
{| class="wikitable"
!bit from lsb
Line 340 ⟶ 367:
|1=FPGA configured
|}
SDRAM must be disabled (REG_CFG & 1 must be zero).
=== 0x0804004C (REG_CRC) ===
Read only? on REG_CFG&1==0
{| class="wikitable"
!bit from lsb
!description
|-
|15-12
|HW major version?
|-
|11-0
|?
|}
SDRAM must be disabled (REG_CFG & 1 must be zero).
This register seems not related to "Cyclic Redundancy Check".
=== 0x08040050 ===
Write only? on REG_CFG&1==0
TBA
SDRAM must be disabled (REG_CFG & 1 must be zero).
=== 0x08040054 ===
Write only on REG_CFG&1==0 ?
TBA
SDRAM must be disabled (REG_CFG & 1 must be zero).
== ED64 Boot ROM Header ==
You can read boot ROM header by:
* set <code>REG_CFG &= ~1</code> (disable SDRAM)
* read from cart usually (by <code>*(uint32_t*)0xB0000000</code> etc, or use PI DMA)
{| class="wikitable"
!PI address
!bytes
!description
|-
|0x10000020
|12
|"ED64 SD boot", can be used to identify SD is usable or not (=SPI)
|-
|0x10000038
|2
|assembly date in FAT style
|-
|0x1000003A
|2
|assembly time in 2-seconds from 00:00:00, ex. 0x5878 for 12:34:56
|-
|0x1000003C
|2
|serial number (16bit binary, hex)
|}
They are, of course, big endian.
{| class="wikitable"
|+Date in FAT Style
!bit from lsb
!description
|-
|15-9
|year - 1980
|-
|8-5
|month (start from 1)
|-
|4-0
|day (start from 1)
|}
== USB Serial Communication ==
| |||