COP1: Difference between revisions
→Full Mode vs Half Mode
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| Single || S || 32 bit float
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| Double || D || 64 bit
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| Word || W || 32 bit integer
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* Perform operation
* Set "Cause: Inexact"
* If "Enable: Inexact" is true, fire exception. Otherwise, set "Flag: Inexact" and put result value into destination register.
This means that Cause be looked at to see the result of the directly preceding instruction. Flags however are cumulative: They are true if any instruction since the last clear signaled that exception, assuming the exception was disabled.
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| 1 || 0 || 0 || "Negative zero", which is considered equal to regular zero
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| any || 0 || != 0 || Denormal/subnormal
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| 0 || 0xFF || 0 || Positive Infinity
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Knowing this, determining special cases and certain operations can be done through simple bit operations:
<code><pre>
fn is_zero(f: u32) -> bool { f & 0x7FFF_FFFF == 0 }
fn is_subnormal(f: u32) -> bool { ((f & 0x7F80_0000) == 0) && ((f & 0x7F_FFFF) != 0) }
fn is_nan(f: u32) -> bool { ((f & 0x7F80_0000) == 0x7F80_0000) && ((f & 0x7F_FFFF) != 0) }
fn is_quiet_nan(f: u32) -> bool { (f & 0x7FC0_0000) == 0x7FC0_0000) }
fn absolute_value(f: u32) -> bool { f & 0x7FFF_FFFF }
fn negate(f: u32) -> bool { f ^ 0x8000_0000 }
</pre></code>
== Special Cases ==
The COP1 will never on its own produce either a subnormal or a qNAN.
The following rules applies to calculating instructions (ADD.X, SUB.X, DIV.X, MUL.X, SQRT.X, ABS, NEG.X, CVT.Y.X, ROUND.Y.X, TRUNC.Y.X, FLOOR.Y.X, CEIL.Y.X, where X is S/D):
* If an input is sNAN, fire Unimplemented Operation
* If an input is subnormal, fire Unimplemented Operation
* If an input is qNAN, signal Invalid Operation and set result to sNAN (specifically 0x7FBFFFFF (for floats) or 0x7FF7FFFFFFFFFFFF (for doubles)) (exceptions: CVT.W.x and CVT.L.x also fire Unimplemented Operation as NAN can not be represented as an integer)
* Perform the operation
* If the operation underflowed, the following happens:
** If "Flush Denorm To Zero" is 1 AND "Enable: Underflow" is 0 AND "Enable: Inexact" is 0, the result is flushed and Underflow and Inexact are signaled. In most cases this means that it is set to 0 or "negative 0". (Two exception: If the rounding mode is "Ceil" and the result is positive, it will be set to the smallest positive value instead; similarly, "Floor" will set a negative result to the negative value that is closest to 0).
** Otherwise, fire Unimplemented Operations
* If the operation is invalid (for example: Infinity-Infinity, 0.0 / 0.0 or SQRT(-2)), set result to sNAN (specifically 0x7FBFFFFF (for floats) or 0x7FF7FFFFFFFFFFFF (for doubles)) and signal Invalid Operation is signaled.
* If the operation was a division by zero, signal division by zero
* If the operation overflowed, signal Overflow and Inexact and set result to Infinite or -Infinity
* If the operation was inexact, signal inexact
MOV.S and MOV.D are special: They just copy the bits and never fire or signal exceptions. They also don't clear the Cause bits.
== Comparisons ==
The COP1 in total has 16 single compare instructions with some pretty confusing names (and another 16 for doubles). The 16 instructions are all possible combinations of the following 4 bits:
* Unordered (Bit 0): Comparison is considered true if one or both of the operands is NAN
* Equal (Bit 1): Comparison is considered true if both operands are equal (note that 0 is equal to -0, but NAN is always different from another NAN)
* Smaller (Bit 2): Comparison is considered true if the first operand is smaller than the second
* SignalOnSNAN (Bit 3): If either operand is sNAN, this will signal Invalid Operation.
If multiple bits are set, the conditions are ORed together: For example, UEQ is considered true if the two operands are equal or unordered.
Note that inputs of qNAN always signal Invalid Operation. Using all bit combinations, this gives the following instructions:
{| class="wikitable"
|+ Compare encoding
|-
! SignalOnSNAN (Bit 3) !! Smaller (Bit 2) || Equal (Bit 1) || Unordered (Bit 0) || Name || Result formula || Invalid Operation Condition
|-
| 0 || 0 || 0 || 0 || F || Result = false || IsQNAN(arg1) OR isQNAN(arg2)
|-
| 0 || 0 || 0 || 1 || UN || Result = unordered(arg1, arg2) || IsQNAN(arg1) OR isQNAN(arg2)
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| 0 || 0 || 1 || 0 || EQ || Result = arg1 == arg2 || IsQNAN(arg1) OR isQNAN(arg2)
|-
| 0 || 0 || 1 || 1 || UEQ || Result = unordered(arg1, arg2) OR (arg1 == arg2) || IsQNAN(arg1) OR isQNAN(arg2)
|-
| 0 || 1 || 0 || 0 || OLT || Result = arg1 < arg2 || IsQNAN(arg1) OR isQNAN(arg2)
|-
| 0 || 1 || 0 || 1 || ULT || Result = unordered(arg1, arg2) OR (arg1 < arg2) || IsQNAN(arg1) OR isQNAN(arg2)
|-
| 0 || 1 || 1 || 0 || OLE || Result = arg1 <= arg2 || IsQNAN(arg1) OR isQNAN(arg2)
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| 0 || 1 || 1 || 1 || ULE || Result = unordered(arg1, arg2) OR (arg1 <= arg2) || IsQNAN(arg1) OR isQNAN(arg2)
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| 1 || 0 || 0 || 0 || SF || Result = false || IsNAN(arg1) OR isNAN(arg2)
|-
| 1 || 0 || 0 || 1 || NGLE || Result = unordered(arg1, arg2) || IsNAN(arg1) OR isNAN(arg2)
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| 1 || 0 || 1 || 0 || SEQ || Result = arg1 == arg2 || IsNAN(arg1) OR isNAN(arg2)
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| 1 || 0 || 1 || 1 || NGL || Result = unordered(arg1, arg2) OR (arg1 == arg2) || IsNAN(arg1) OR isNAN(arg2)
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| 1 || 1 || 0 || 0 || LT || Result = arg1 < arg2 || IsNAN(arg1) OR isNAN(arg2)
|-
| 1 || 1 || 0 || 1 || NGE || Result = unordered(arg1, arg2) OR (arg1 < arg2) || IsNAN(arg1) OR isNAN(arg2)
|-
| 1 || 1 || 1 || 0 || LE || Result = arg1 <= arg2 || IsNAN(arg1) OR isNAN(arg2)
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| 1 || 1 || 1 || 1 || NGT || Result = unordered(arg1, arg2) OR (arg1 <= arg2) || IsNAN(arg1) OR isNAN(arg2)
|}
== Full Mode vs Half Mode ==
The COP1 can run in one of two modes, which is controlled via COP0.Status Bit 26. In "Full Mode", the COP1 has 32 bit registers that are each 64 bits wide are available. In "Half Mode", only the 16 even registers are legal to be used; using odd numbered registers is considered undefined behavior.
Older software usually ran in "Half Mode". A reason for that could be that context switches (for multithreading) can be performed more cheaply, as only 16 FPU registers need to be stored.
When using "Half Mode" it is important to not use any FPU registers with odd indices. For compiled code this has to be configured accordingly ("+nooddspreg" in clang).
''The remainder of this section documents undefined behavior. Skip this unless you are an emulator developer who cares about accuracy a little bit too much.''
If software decides to use odd indices in "Half Mode", different things happen, depending on the instruction:
{| class="wikitable"
|+ Illegal register indexing in "Half Mode" (normally undocumented behavior - do not use)
|-
! Actual Register Index || MFC1/MTC1/LWC1/LDC1 || fd (32 bit), ft (32 bit) or any 64 bit || fs (32 bit)
|-
| 0 || 1 (high 32 bits) / 0 (low 32 bits) || 0 (low 32 bits) || 0 or 1
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| 1 || unused || 1 (low 32 bits) || unused
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| 2 || 3 (high 32 bits) / 2 (low 32 bits) || 2 (low 32 bits) || 2 or 3
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| 3 || unused || 3 (low 32 bits) || unused
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| 4 || 5 (high 32 bits) / 4 (low 32 bits) || 4 (low 32 bits) || 4 or 5
|-
| 5 || unused || 5 (low 32 bits) || unused
|}
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