64DD/Interface

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The 64DD Interface is the only interface to the 64DD hardware, such as the drive, real-time clock, and more. All memory-mapped registers on 64DD only use the high 16-bit word, the low 16-bit word only returns 0000.

Registers

Table Notation:

R = Readable bit
W = Writable bit
U = Undefined/Unused bit
-n = Default value n at power on
[x:y] = Specifies bits x to y, inclusively

0x0500 0500 - ASIC_DATA


ASIC_DATA 0x0500 0500
31:24 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
DATA[15:8]
23:16 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
DATA[7:0]
15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
bit 31-16 DATA[15:0]: Used as argument for commands, and used to return a value after a command is issued.

0x0500 0504 - ASIC_MISC_REG


ASIC_MISC_REG 0x0500 0504
31:24 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
MISC_REG[15:8]
23:16 R-0 R-0 R-0 R-0 R-0 R-1 R-0 R-1
MISC_REG[7:0]
15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
bit 31-16 MISC_REG[15:0]: Unknown, on a retail 64DD drive, it returns the value 0005.

0x0500 0508 - ASIC_STATUS (R) / ASIC_CMD (W)


When Reading:

ASIC_STATUS 0x0500 0508
31:24 U-0 R-0 U-0 R-0 R-0 R-0 R-0 R-0
DATA_REQ C2_XFER BM_ERROR BM_INT MECHA_INT DISK
23:16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
BUSY RESET SPM_OFF HEAD_RETRACT WPROTECT_ERR MECHA_ERROR DISK_CHANGE
15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
bit 30 DATA_REQ: When reading from disk, this would be set to 1 when the data is ready to be read from the buffer, and when writing to disk, this would be set to 1 when the drive asks for the data to be written.
bit 28 C2_XFER: When reading from disk, this would be set to 1 when all 4 C2 sector data are read into the buffer.
bit 27 BM_ERROR: This bit is set to 1 when the Buffer Manager has an error.
bit 26 BM_INT: This bit is set to 1 when the Buffer Manager issues an interrupt. (Reading the register considers this specific interrupt as acknowledged.)
bit 25 MECHA_INT: This bit is set to 1 when the drive controller (H8/300 CPU) issues an interrupt. (Generally after any command issued is processed.)
bit 24 DISK: Disk is inserted.
bit 23 BUSY: If set to 1, the drive controller is currently busy either initializing, or currently processing a command.
bit 22 RESET: If set to 1, the drive is considered in Reset mode. (It is recommended to disable that mode.)
bit 20 SPM_OFF: If set to 1, the Spindle Motor is considered OFF.
bit 19 HEAD_RETRACT: If set to 1, the Drive Head is retracted.
bit 18 WPROTECT_ERR: Write Protect Error. (Set to 1 when attempting to write a write protected zone.)
bit 17 MECHA_ERROR: If set to 1, then the processed command ended in error.
bit 16 DISK_CHANGE: Set to 1 any time a disk has been inserted at least once (including at power on). It is NOT reset after a disk has been removed.

For detecting the 64DD, this register is read and checked if the first 16-bit word is 0000, if not then the 64DD is considered not present.

When Writing:

ASIC_CMD 0x0500 0508
31:24 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
CMD[15:8]
23:16 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
CMD[7:0]
15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
bit 31-16 CMD[15:0]: Writing to this register would issue a command.

0x0500 050C - ASIC_CUR_TK


ASIC_CUR_TK 0x0500 050C
31:24 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
INDEX_LOCK HEAD TRACK[11:8]
23:16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TRACK[7:0]
15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
bit 30-29 INDEX_LOCK: If 11, then the head is locked to the track and could be accessed.
bit 28 HEAD: Current Head (0 or 1)
bit 27-16 TRACK[11:0]: Current Cylinder Track

0x0500 0510 - ASIC_BM_STATUS (R) / ASIC_BM_CTL (W)


When Reading:

ASIC_BM_STATUS 0x0500 0510
31:24 R-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
RUNNING ERROR MICRO_STATUS BLOCKS
23:16 R-0 R-0 R-0 U-0 U-0 U-0 U-0 R-0
C1_CORRECT C1_DOUBLE C1_SINGLE C1_ERROR
15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
bit 31 RUNNING: If set to 1, then the Buffer Manager is currently running.
bit 26 ERROR: Buffer Manager Error State
bit 25 MICRO_STATUS: Micro Sequencer Error State? (Used to recognize as an error.)
bit 24 BLOCKS: If set to 1, it's in BLOCK mode where an entire cylinder track is read.
bit 23 C1_CORRECT: (Unconfirmed) Sector has been corrected by C1 error correction.
bit 22 C1_DOUBLE: Sector has 2 errors, detected with C1 error correction.
bit 21 C1_SINGLE: Sector has 1 error, detected with C1 error correction.
bit 16 C1_ERROR: Sector couldn't be corrected with C1 error correction.

When Writing:

ASIC_BM_CTL 0x0500 0510
31:24 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
START_BM BM_MODE BM_INT_MASK BM_RESET BM_DISABLE_OR_CHK BM_DISABLE_C1 BM_XFERBLKS BM_MECHA_INT_RESET
23:16 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
SECTOR[7:0]
15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
bit 31 START_BM: If set to 1, then the Buffer Manager should be running.
bit 30 BM_MODE: If set to 1, the Buffer Manager is set to Read Mode, else it's set to Write Mode.
bit 29 BM_INT_MASK: (Unconfirmed) If set to 1, then Buffer Manager interrupts are masked.
bit 28 BM_RESET: If set to 1, resets the Buffer Manager.
bit 27 BM_DISABLE_OR_CHK: (Unconfirmed)
bit 26 BM_DISABLE_C1: (Unconfirmed) Disables C1 Error Correction?
bit 25 BM_XFERBLKS: If set to 1, processes the entire cylinder track.
bit 24 BM_MECHA_INT_RESET: If set to 1, acknowledges and resets the MECHA_INT Command interrupt.
bit 23-16 SECTOR[7:0]: Sector to start processing with

0x0500 0514 - ASIC_ERR_SECTOR


ASIC_ERR_SECTOR 0x0500 0514
31:24 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
AM_FAIL MICRO_FAIL SPINDLE_FAIL OVER_RUN OFFTRACK NO_DISK CLOCK_UNLOCK SELF_STOP
23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
bit 31 AM_FAIL: ?
bit 30 MICRO_FAIL: ?
bit 29 SPINDLE_FAIL: ?
bit 28 OVER_RUN: ?
bit 27 OFFTRACK: ?
bit 26 NO_DISK: If set to 1, disk is not inserted.
bit 25 CLOCK_UNLOCK: ?
bit 24 SELF_STOP: ?

0x0500 0518 - ASIC_SEQ_STATUS (R) / ASIC_SEQ_CTL (W)


ASIC_SEQ_STATUS / ASIC_SEQ_CTL 0x0500 0518
31:24 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
MICRO_INT_MASK MICRO_PC_ENABLE
23:16 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
bit 31 MICRO_INT_MASK: (Unconfirmed)
bit 30 MICRO_PC_ENABLE: If set to 1, enable Micro Sequencer. Set to 0 to disable.

0x0500 051C - ASIC_CUR_SECTOR (R)


ASIC_CUR_SECTOR 0x0500 051C
31:24 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
SECTOR[7:0]
23:16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
bit 31-24 SECTOR[7:0]: (Unconfirmed) Current Sector

0x0500 0520 - ASIC_HARD_RESET (W)


ASIC_HARD_RESET 0x0500 0520
31:24 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
RESET[15:8]
23:16 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
RESET[7:0]
15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
bit 31-16 RESET[15:0]: Write AAAA to reset the 64DD hardware. Reset mode would be enabled after some reinitialization time.