Reality Signal Processor/CPU Core: Difference between revisions

| rowspan="4" |Scalar
|0x00
|<code>LBV</code> / <code>SBV</code>
|Load / Store 1 byte into/from a VPR
|-
|0x01
|<code>LSV</code> / <code>SSV</code>
|Load / Store 2 bytes into/from a VPR
|-
|0x02
|<code>LLV</code> / <code>SLV</code>
|Load / Store 4 bytes into/from a VPR
|-
|0x03
|<code>LDV</code> / <code>SDV</code>
|Load / Store 4 bytes into/from a VPR
|-
| rowspan="4" |128-bit
|0x04
|<code>LQV</code>
|Load (up to) 16 bytes into a VPR, left-aligned
|-
|0x05
|<code>LRV</code>
|Load (up to) 16 bytes into a VPR, right-aligned
|-
|0x04
|<code>SQV</code>
|Store (up to) 16 bytes from a VPR, left-aligned
|-
|0x05
|<code>SRV</code>
|Store (up to) 16 bytes from a VPR, right-aligned
|-
| rowspan="4" |8-bit packed
|0x06
|<code>LPV</code> / <code>SPV</code>
|Load / store 8 8-bit signed values into a VPR
|-
|0x07
|<code>LUV</code> / <code>SUV</code>
|Load / store 8 8-bit unsigned values into a VPR
|-
|0x08
|<code>LHV</code> / <code>SHV</code>
|Load / store 8 8-bit unsigned values into VPR, accessing every other byte in memory
|-
|0x09
|<code>LFV</code> / <code>SFV</code>
|Load / store 4 8-bit unsigned values into VPR, accessing every fourth bytes in memory
|-
| rowspan="3" |Transpose
|0x01
|<code>SWV</code>
|
|-
|0x0B
|<code>LTV</code>
|Load 8 lanes from 8 GPRs into a VPR
|-
|0x0B
|<code>STV</code>
|Store 8 lanes of a VPR into 8 GPRs
|}