User contributions for Rasky
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9 June 2022
- 14:1414:14, 9 June 2022 diff hist +15 PIF-NUS →IPL3 checksum algorithm current
- 14:1414:14, 9 June 2022 diff hist +26 PIF-NUS →IPL3 checksum algorithm
- 14:1314:13, 9 June 2022 diff hist +132 PIF-NUS →IPL3 checksum algorithm
8 June 2022
- 20:2720:27, 8 June 2022 diff hist −9 PIF-NUS →IPL3 checksum algorithm Tag: Visual edit
- 20:2520:25, 8 June 2022 diff hist −148 PIF-NUS →IPL3 checksum algorithm
- 20:1420:14, 8 June 2022 diff hist +91 PIF-NUS →IPL3 checksum algorithm
- 09:4809:48, 8 June 2022 diff hist +2 Video Interface →0x0440 0000 - VI_CTRL
- 09:4709:47, 8 June 2022 diff hist 0 Video Interface →0x0440 0000 - VI_CTRL
- 09:4609:46, 8 June 2022 diff hist +698 Video Interface →0x0440 0000 - VI_CTRL
24 May 2022
- 21:3821:38, 24 May 2022 diff hist +1,546 Reality Signal Processor/Interface →SP_DMA_RDLEN current Tag: Visual edit: Switched
15 May 2022
- 13:5613:56, 15 May 2022 diff hist 0 PIF-NUS →RAM-based communication protocol Tag: Visual edit
- 13:5513:55, 15 May 2022 diff hist +36 PIF-NUS →RAM-based communication protocol Tag: Visual edit
- 13:5413:54, 15 May 2022 diff hist +29 PIF-NUS →RAM-based communication protocol Tag: Visual edit
- 13:5313:53, 15 May 2022 diff hist +356 PIF-NUS →IPL2 checksum algorithm Tag: Visual edit
- 13:0813:08, 15 May 2022 diff hist +34 PIF-NUS →Console startup Tag: Visual edit
- 13:0713:07, 15 May 2022 diff hist +66 PIF-NUS →Console startup Tag: Visual edit
- 13:0613:06, 15 May 2022 diff hist +10 PIF-NUS →Console startup Tag: Visual edit
- 13:0413:04, 15 May 2022 diff hist +1,769 PIF-NUS →Console startup Tag: Visual edit
- 12:5012:50, 15 May 2022 diff hist +1,760 PIF-NUS No edit summary Tag: Visual edit
10 May 2022
- 09:5809:58, 10 May 2022 diff hist +3 Memory map →Range 0x0400'0000 - 0x04FF'FFFF (RCP registers) current Tag: Visual edit
- 07:5407:54, 10 May 2022 diff hist +23 Memory map →Physical Memory Map accesses Tag: Visual edit
- 07:3607:36, 10 May 2022 diff hist −241 Reality Signal Processor/Interface →DMEM and IMEM Tag: Visual edit
4 May 2022
- 09:5809:58, 4 May 2022 diff hist +227 PIF-NUS →RAM-based communication protocol Tag: Visual edit
30 April 2022
- 08:2208:22, 30 April 2022 diff hist +55 Memory map No edit summary Tag: Visual edit
28 April 2022
- 20:1020:10, 28 April 2022 diff hist +164 Memory map →Ranges 0x0500'0000 - 0x1FBF'FFFF and 0x1FD0'0000 - 0x7FFF'FFFF (PI external bus) Tag: Visual edit
26 April 2022
- 08:2108:21, 26 April 2022 diff hist +37 Memory map →Physical Memory Map accesses Tag: Visual edit
25 April 2022
- 23:0623:06, 25 April 2022 diff hist +61 Memory map →Physical Memory Map Tag: Visual edit
- 23:0123:01, 25 April 2022 diff hist −1 Memory map →Other ranges 0x0500'0000 - 0x7FFF'FFFF (External bus via PI) Tag: Visual edit
- 22:5822:58, 25 April 2022 diff hist −32 Memory map →Other ranges 0x0500'0000 - 0x7FFF'FFFF (External bus via PI) Tag: Visual edit
- 22:5622:56, 25 April 2022 diff hist +41 Memory map →Other ranges 0x0500'0000 - 0x7FFF'FFFF (External bus via PI) Tag: Visual edit
- 22:5222:52, 25 April 2022 diff hist +194 Memory map →Memory Map accesses Tag: Visual edit
- 21:2421:24, 25 April 2022 diff hist +50 Memory map →Physical Memory Map
- 20:5720:57, 25 April 2022 diff hist +55 Memory map →All other ranges 0x0500'0000 - 0xFFFF'FFFF (External SysAD bus via PI)
- 20:5520:55, 25 April 2022 diff hist +130 Memory map →All other ranges 0x0500'0000 - 0xFFFF'FFFF (External SysAD bus via PI)
- 20:4220:42, 25 April 2022 diff hist +26 Memory map →Memory Map accesses Tag: Visual edit
- 20:4120:41, 25 April 2022 diff hist +16 Memory map →Memory Map accesses Tag: Visual edit
- 20:3820:38, 25 April 2022 diff hist +47 Memory map No edit summary
- 20:3620:36, 25 April 2022 diff hist +3,790 Memory map No edit summary Tag: Visual edit
- 10:0310:03, 25 April 2022 diff hist +2,615 Memory map No edit summary Tag: Visual edit
5 April 2022
- 21:2221:22, 5 April 2022 diff hist +403 Reality Signal Processor/CPU Core →128-bit vector loads: LQV, LRV current Tag: Visual edit
- 21:1221:12, 5 April 2022 diff hist +2 Reality Signal Processor/CPU Core →128-bit vector loads: LQV, LRV Tag: Visual edit
- 21:1121:11, 5 April 2022 diff hist +376 Reality Signal Processor/CPU Core →Usage Tag: Visual edit
- 17:1117:11, 5 April 2022 diff hist +3,525 Reality Signal Processor/CPU Core No edit summary Tag: Visual edit
- 16:4516:45, 5 April 2022 diff hist −30 Reality Signal Processor/CPU Core No edit summary Tag: Visual edit
- 16:4516:45, 5 April 2022 diff hist −6 Reality Signal Processor/CPU Core →Instruction details Tag: Visual edit
- 16:4416:44, 5 April 2022 diff hist +245 Reality Signal Processor/CPU Core →Instruction details Tag: Visual edit
- 16:4216:42, 5 April 2022 diff hist −496 Reality Signal Processor/CPU Core →Instruction details Tag: Visual edit
- 16:3816:38, 5 April 2022 diff hist +6,096 Reality Signal Processor/CPU Core No edit summary Tag: Visual edit
- 07:3507:35, 5 April 2022 diff hist +364 Reality Signal Processor/CPU Core →Broadcast modifier Tag: Visual edit
- 07:3307:33, 5 April 2022 diff hist 0 Reality Signal Processor/CPU Core →Select instructions Tag: Visual edit
- 07:3207:32, 5 April 2022 diff hist +117 Reality Signal Processor/CPU Core →Single-lane instructions Tag: Visual edit
4 April 2022
- 16:3016:30, 4 April 2022 diff hist +10 Reality Signal Processor/CPU Core →VU/SU Moves Tag: Visual edit
- 16:2316:23, 4 April 2022 diff hist −6 Reality Signal Processor/CPU Core →Control registers Tag: Visual edit
- 15:1815:18, 4 April 2022 diff hist 0 Reality Signal Processor/CPU Core →Loads and stores Tag: Visual edit
- 15:1715:17, 4 April 2022 diff hist +2,574 Reality Signal Processor/CPU Core No edit summary Tag: Visual edit
- 14:4814:48, 4 April 2022 diff hist +299 Reality Signal Processor/CPU Core →Loads and stores Tag: Visual edit
- 14:3614:36, 4 April 2022 diff hist −1 Reality Signal Processor/CPU Core →Loads and stores Tag: Visual edit
- 14:3114:31, 4 April 2022 diff hist +51 Reality Signal Processor/CPU Core →Single-lane instructions Tag: Visual edit
- 14:2814:28, 4 April 2022 diff hist +438 Reality Signal Processor/CPU Core →Single-lane instructions Tag: Visual edit
- 14:0014:00, 4 April 2022 diff hist +70 Reality Signal Processor/CPU Core →Single-lane instructions Tag: Visual edit
- 13:5613:56, 4 April 2022 diff hist +131 Reality Signal Processor/CPU Core →Single-lane instructions Tag: Visual edit
- 13:5113:51, 4 April 2022 diff hist +491 Reality Signal Processor/CPU Core →Computational instructions Tag: Visual edit
- 13:4513:45, 4 April 2022 diff hist +524 Reality Signal Processor/CPU Core →Broadcast modifier Tag: Visual edit
- 08:5108:51, 4 April 2022 diff hist +2,652 Reality Signal Processor/CPU Core No edit summary Tag: Visual edit
3 April 2022
- 23:2423:24, 3 April 2022 diff hist +4,421 Reality Signal Processor/CPU Core →Opcodes Tag: Visual edit
- 23:1223:12, 3 April 2022 diff hist +3,529 Reality Signal Processor/CPU Core →Vector Unit (VU) Tag: Visual edit
- 22:4622:46, 3 April 2022 diff hist +1,711 Reality Signal Processor/CPU Core No edit summary Tag: Visual edit
- 22:3922:39, 3 April 2022 diff hist −155 Reality Coprocessor No edit summary current Tag: Visual edit
- 22:3722:37, 3 April 2022 diff hist +1,172 Reality Coprocessor →RCP Interface Tag: Visual edit
- 22:3722:37, 3 April 2022 diff hist +341 Reality Signal Processor No edit summary current Tag: Visual edit
- 22:2822:28, 3 April 2022 diff hist +43 Reality Coprocessor No edit summary Tag: Visual edit
30 March 2022
- 21:5121:51, 30 March 2022 diff hist +3,799 Serial Interface No edit summary current
- 20:3320:33, 30 March 2022 diff hist −4 PIF-NUS →Pinout Tag: Visual edit
- 16:3116:31, 30 March 2022 diff hist +158 Serial Interface →0x0480 0014 - SI_PIF_AD_RD4B Tag: Visual edit
- 16:2916:29, 30 March 2022 diff hist +2,347 Serial Interface No edit summary Tag: Visual edit
- 07:5507:55, 30 March 2022 diff hist +6 Serial Interface →0x0480 0018 - SI_STATUS
- 07:5307:53, 30 March 2022 diff hist +1,474 Serial Interface No edit summary
29 March 2022
- 23:0423:04, 29 March 2022 diff hist 0 PIF-NUS →Pinout Tag: Visual edit
- 22:5322:53, 29 March 2022 diff hist +21 PIF-NUS →RAM-based communication protocol Tag: Visual edit
- 22:5122:51, 29 March 2022 diff hist +2,858 PIF-NUS No edit summary Tag: Visual edit
- 21:5721:57, 29 March 2022 diff hist −4 PIF-NUS No edit summary Tag: Visual edit
- 21:5621:56, 29 March 2022 diff hist +1,146 PIF-NUS No edit summary
- 21:5521:55, 29 March 2022 diff hist −1,357 CIC-NUS →PIF
- 21:4921:49, 29 March 2022 diff hist +419 PIF-NUS →Console startup Tag: Visual edit
- 21:4521:45, 29 March 2022 diff hist +6,345 N CIC-NUS Created page with "==== CIC ==== '''Disclaimer: All of the CIC actions described below have been done successfully as part of a University project. Some of the details are missing whether it was to avoid encouraging piracy, simply not required for the core of the paper or lost in the language translation (authors live in Germany) is unknown.''' alt=CIC decap pins labeled|thumb|'''CIC decap pins labeled''' {| class="wikitable" |+CIC/IPL variants !Variant !..."
- 21:4521:45, 29 March 2022 diff hist −7,061 PIF-NUS No edit summary
- 21:4421:44, 29 March 2022 diff hist +2,809 PIF-NUS No edit summary Tag: Visual edit
- 21:2921:29, 29 March 2022 diff hist +39 N Sharp SM5 Rasky moved page Sharp SM5 to Sharp SM5 Microcontroller current Tag: New redirect
- 21:2921:29, 29 March 2022 diff hist 0 m Sharp SM5 Microcontroller Rasky moved page Sharp SM5 to Sharp SM5 Microcontroller current
- 21:2821:28, 29 March 2022 diff hist +675 N Sharp SM5 Microcontroller Created page with "The PIF and CIC (inside the cartridge) are both custom versions of Sharp SM5 4-bit microcontrollers. These microcontrollers were also used in the Game & Watch handheld games, so Nintendo already had developers that were familiar with them. While the core functionality of the PIF and CIC are generally understood, the microcontroller model is custom and therefore not well known. There has been some effort to reverse engineer the PIF and CIC communication to..." Tag: Visual edit
- 20:5120:51, 29 March 2022 diff hist +192 Reality Signal Processor/Interface No edit summary
- 20:4820:48, 29 March 2022 diff hist +21 Reality Signal Processor/Interface →SP_SEMAPHORE
- 16:4116:41, 29 March 2022 diff hist −1 Reality Signal Processor/Interface No edit summary
- 16:4016:40, 29 March 2022 diff hist −119 Reality Signal Processor/Interface No edit summary Tag: Visual edit
- 16:3816:38, 29 March 2022 diff hist +607 Reality Signal Processor/Interface No edit summary Tag: Visual edit
- 16:3416:34, 29 March 2022 diff hist +114 Reality Signal Processor/Interface No edit summary
28 March 2022
- 23:4523:45, 28 March 2022 diff hist +2 Reality Signal Processor/Interface →SP_STATUS Tag: Visual edit
- 23:4423:44, 28 March 2022 diff hist +2 Reality Signal Processor/Interface →SP_STATUS Tag: Visual edit
- 23:3523:35, 28 March 2022 diff hist +10 Reality Signal Processor/Interface No edit summary
- 23:3223:32, 28 March 2022 diff hist +34 Reality Signal Processor/Interface No edit summary Tag: Visual edit
- 23:3123:31, 28 March 2022 diff hist +292 Reality Signal Processor/Interface No edit summary Tag: Visual edit
- 23:2123:21, 28 March 2022 diff hist +414 Reality Signal Processor/Interface No edit summary Tag: Visual edit
- 23:0823:08, 28 March 2022 diff hist +232 Reality Signal Processor/Interface →RSP Internal Registers
- 23:0223:02, 28 March 2022 diff hist +5,646 Reality Signal Processor/Interface →DMA transfers Tag: Visual edit: Switched
- 15:0615:06, 28 March 2022 diff hist 0 Reality Signal Processor/Interface No edit summary
- 14:5614:56, 28 March 2022 diff hist +23 Reality Signal Processor/Interface →SP_SEMAPHORE
- 14:5514:55, 28 March 2022 diff hist +1 Reality Signal Processor/Interface →SP_SEMAPHORE
- 14:5514:55, 28 March 2022 diff hist 0 Reality Signal Processor/Interface →SP_SEMAPHORE
- 14:5514:55, 28 March 2022 diff hist 0 Reality Signal Processor/Interface →SP_SEMAPHORE
- 14:5414:54, 28 March 2022 diff hist +3,501 Reality Signal Processor/Interface No edit summary
- 14:3314:33, 28 March 2022 diff hist +995 Reality Signal Processor/Interface No edit summary Tag: Visual edit: Switched
- 14:1614:16, 28 March 2022 diff hist +3,245 Reality Signal Processor/Interface No edit summary Tag: Visual edit: Switched
- 13:5513:55, 28 March 2022 diff hist −1 Reality Signal Processor/Interface →SP_STATUS
- 13:5313:53, 28 March 2022 diff hist +867 Reality Signal Processor/Interface →SP_STATUS Tag: Visual edit
- 13:4513:45, 28 March 2022 diff hist +4,582 Reality Signal Processor/Interface No edit summary Tag: Visual edit: Switched
- 13:0913:09, 28 March 2022 diff hist +138 Memory map No edit summary Tag: Visual edit
- 12:3412:34, 28 March 2022 diff hist +1,115 PIF-NUS No edit summary Tag: Visual edit
27 March 2022
- 22:1322:13, 27 March 2022 diff hist +2 Reality Signal Processor/Interface →DMA transfers Tag: Visual edit
- 22:0722:07, 27 March 2022 diff hist −26 Reality Signal Processor/Interface →DMA transfers Tag: Visual edit
- 21:5421:54, 27 March 2022 diff hist +2 Reality Signal Processor/Interface →DMA transfers Tag: Visual edit
- 21:5321:53, 27 March 2022 diff hist +2 Reality Signal Processor/Interface No edit summary
- 21:5221:52, 27 March 2022 diff hist +2 Reality Signal Processor/Interface →SP_PC Tag: Visual edit: Switched
- 21:5021:50, 27 March 2022 diff hist +1,579 Reality Signal Processor/Interface →RSP Internal Registers Tag: Visual edit: Switched
- 21:4121:41, 27 March 2022 diff hist +6 Reality Signal Processor/Interface →Register details Tag: Visual edit
- 21:4021:40, 27 March 2022 diff hist +1,205 Reality Signal Processor/Interface No edit summary Tag: Visual edit
- 20:5720:57, 27 March 2022 diff hist +510 Reality Signal Processor/Interface →RSP Internal Registers Tag: Visual edit
- 20:4520:45, 27 March 2022 diff hist +516 Reality Signal Processor/Interface No edit summary Tag: Visual edit: Switched
- 20:3320:33, 27 March 2022 diff hist +3,208 N Reality Signal Processor/Interface Created page with "The RSP interface is accessed by VR4300 via memory mapped registers at the physical address 0x040x xxxx. == DMEM and IMEM == Both RSP memory banks are fully memory mapped into the VR4300 address space, as follows: {| class="wikitable" ! colspan="2" |Address range !Memory |- |0x04000000 |0x04000FFF |RSP DMEM |- |0x04001000 |0x04001FFF |RSP IMEM |} Access must be performed using 32-bit reads and writes. '''TODO:''' document exact behavior on different access sizes. Since..." Tag: Visual edit: Switched
- 20:0920:09, 27 March 2022 diff hist +233 ROM Header No edit summary Tag: Visual edit
- 14:5314:53, 27 March 2022 diff hist +137 ROM Header No edit summary Tag: Visual edit
- 13:4513:45, 27 March 2022 diff hist +7 ROM Header No edit summary Tag: Visual edit
- 13:0313:03, 27 March 2022 diff hist +70 ROM Header No edit summary Tag: Visual edit
- 11:5911:59, 27 March 2022 diff hist +2,241 N Reality Signal Processor/CPU Core Created page with "== Scalar unit (SU) == The scalar is the half of the RSP core that is similar to a standard MIPS R4000 32-bit CPU. It has 32 32-bit registers (conventionally called <code>r0</code>-<code>r31</code>) and implement most standard opcodes. This page does not describe the whole scalar unit has standard MIPS documentation suffices, but it highlights the main difference. === Missing opcodes === The following opcodes are not implemented by RSP: * '''Multiplication units.''' RS..." Tag: Visual edit
- 11:3911:39, 27 March 2022 diff hist +404 Reality Signal Processor →RSP CPU core Tag: Visual edit: Switched
- 11:3111:31, 27 March 2022 diff hist +20 Reality Signal Processor No edit summary Tag: Visual edit
- 11:2911:29, 27 March 2022 diff hist +727 Reality Signal Processor No edit summary Tag: Visual edit
26 March 2022
- 23:1823:18, 26 March 2022 diff hist +217 ROM Header No edit summary Tag: Visual edit
- 23:1623:16, 26 March 2022 diff hist +299 ROM Header No edit summary Tag: Visual edit
- 23:0523:05, 26 March 2022 diff hist +117 ROM Header →Standard header Tag: Visual edit
- 23:0223:02, 26 March 2022 diff hist +22 m ROM Header No edit summary Tag: Visual edit
- 22:5822:58, 26 March 2022 diff hist −12 m ROM Header →Support by emulators Tag: Visual edit
- 22:5722:57, 26 March 2022 diff hist −201 ROM Header No edit summary Tag: Visual edit
- 22:5422:54, 26 March 2022 diff hist +4,608 ROM Header No edit summary Tag: Visual edit
- 22:1722:17, 26 March 2022 diff hist +37 ROM Header No edit summary Tag: Visual edit
- 22:1322:13, 26 March 2022 diff hist +287 ROM Header No edit summary Tag: Visual edit
- 21:5321:53, 26 March 2022 diff hist +355 ROM Header No edit summary Tag: Visual edit
- 19:0919:09, 26 March 2022 diff hist +838 ROM Header No edit summary Tag: Visual edit
- 18:5518:55, 26 March 2022 diff hist +1,794 N ROM Header Initial version Tag: Visual edit
- 18:3718:37, 26 March 2022 diff hist +13 m Game Pak No edit summary Tag: Visual edit
- 18:3618:36, 26 March 2022 diff hist +90 m Game Pak No edit summary Tag: Visual edit
14 November 2021
- 10:2010:20, 14 November 2021 diff hist +129 MIPS Interface No edit summary current
- 10:1910:19, 14 November 2021 diff hist +106 MIPS Interface No edit summary Tag: Visual edit: Switched
5 October 2021
- 23:0823:08, 5 October 2021 diff hist +45 Libdragon No edit summary current Tag: Visual edit
- 23:0723:07, 5 October 2021 diff hist +153 Libdragon No edit summary Tag: Visual edit
4 October 2021
- 18:1118:11, 4 October 2021 diff hist +7 Libdragon No edit summary Tag: Visual edit
- 18:1018:10, 4 October 2021 diff hist +1,065 Libdragon No edit summary
- 16:4216:42, 4 October 2021 diff hist 0 Libdragon No edit summary Tag: Visual edit
- 16:4016:40, 4 October 2021 diff hist +714 Libdragon No edit summary Tag: Visual edit
- 13:0313:03, 4 October 2021 diff hist +76 Libdragon No edit summary Tag: Visual edit
- 13:0113:01, 4 October 2021 diff hist +98 Libdragon No edit summary Tag: Visual edit
- 12:5912:59, 4 October 2021 diff hist +2,277 Libdragon Initial version Tag: Visual edit
30 August 2021
- 17:5117:51, 30 August 2021 diff hist +308 N Talk:RDRAM Interface Created page with "--~~~~ (SwapField[8:0] x Adr[19:11]) + ~SwapField[8:0]xAdr[28:20] Does this mean: (SwapField[8:0] & Adr[19:11]) | (~SwapField[8:0] & Adr[28:20]) That is, is the SwapField..."