User contributions for Rasky
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28 March 2022
- 13:5513:55, 28 March 2022 diff hist −1 Reality Signal Processor/Interface →SP_STATUS
- 13:5313:53, 28 March 2022 diff hist +867 Reality Signal Processor/Interface →SP_STATUS Tag: Visual edit
- 13:4513:45, 28 March 2022 diff hist +4,582 Reality Signal Processor/Interface No edit summary Tag: Visual edit: Switched
- 13:0913:09, 28 March 2022 diff hist +138 Memory map No edit summary Tag: Visual edit
- 12:3412:34, 28 March 2022 diff hist +1,115 PIF-NUS No edit summary Tag: Visual edit
27 March 2022
- 22:1322:13, 27 March 2022 diff hist +2 Reality Signal Processor/Interface →DMA transfers Tag: Visual edit
- 22:0722:07, 27 March 2022 diff hist −26 Reality Signal Processor/Interface →DMA transfers Tag: Visual edit
- 21:5421:54, 27 March 2022 diff hist +2 Reality Signal Processor/Interface →DMA transfers Tag: Visual edit
- 21:5321:53, 27 March 2022 diff hist +2 Reality Signal Processor/Interface No edit summary
- 21:5221:52, 27 March 2022 diff hist +2 Reality Signal Processor/Interface →SP_PC Tag: Visual edit: Switched
- 21:5021:50, 27 March 2022 diff hist +1,579 Reality Signal Processor/Interface →RSP Internal Registers Tag: Visual edit: Switched
- 21:4121:41, 27 March 2022 diff hist +6 Reality Signal Processor/Interface →Register details Tag: Visual edit
- 21:4021:40, 27 March 2022 diff hist +1,205 Reality Signal Processor/Interface No edit summary Tag: Visual edit
- 20:5720:57, 27 March 2022 diff hist +510 Reality Signal Processor/Interface →RSP Internal Registers Tag: Visual edit
- 20:4520:45, 27 March 2022 diff hist +516 Reality Signal Processor/Interface No edit summary Tag: Visual edit: Switched
- 20:3320:33, 27 March 2022 diff hist +3,208 N Reality Signal Processor/Interface Created page with "The RSP interface is accessed by VR4300 via memory mapped registers at the physical address 0x040x xxxx. == DMEM and IMEM == Both RSP memory banks are fully memory mapped into the VR4300 address space, as follows: {| class="wikitable" ! colspan="2" |Address range !Memory |- |0x04000000 |0x04000FFF |RSP DMEM |- |0x04001000 |0x04001FFF |RSP IMEM |} Access must be performed using 32-bit reads and writes. '''TODO:''' document exact behavior on different access sizes. Since..." Tag: Visual edit: Switched
- 20:0920:09, 27 March 2022 diff hist +233 ROM Header No edit summary Tag: Visual edit
- 14:5314:53, 27 March 2022 diff hist +137 ROM Header No edit summary Tag: Visual edit
- 13:4513:45, 27 March 2022 diff hist +7 ROM Header No edit summary Tag: Visual edit
- 13:0313:03, 27 March 2022 diff hist +70 ROM Header No edit summary Tag: Visual edit
- 11:5911:59, 27 March 2022 diff hist +2,241 N Reality Signal Processor/CPU Core Created page with "== Scalar unit (SU) == The scalar is the half of the RSP core that is similar to a standard MIPS R4000 32-bit CPU. It has 32 32-bit registers (conventionally called <code>r0</code>-<code>r31</code>) and implement most standard opcodes. This page does not describe the whole scalar unit has standard MIPS documentation suffices, but it highlights the main difference. === Missing opcodes === The following opcodes are not implemented by RSP: * '''Multiplication units.''' RS..." Tag: Visual edit
- 11:3911:39, 27 March 2022 diff hist +404 Reality Signal Processor →RSP CPU core Tag: Visual edit: Switched
- 11:3111:31, 27 March 2022 diff hist +20 Reality Signal Processor No edit summary Tag: Visual edit
- 11:2911:29, 27 March 2022 diff hist +727 Reality Signal Processor No edit summary Tag: Visual edit
26 March 2022
- 23:1823:18, 26 March 2022 diff hist +217 ROM Header No edit summary Tag: Visual edit
- 23:1623:16, 26 March 2022 diff hist +299 ROM Header No edit summary Tag: Visual edit
- 23:0523:05, 26 March 2022 diff hist +117 ROM Header →Standard header Tag: Visual edit
- 23:0223:02, 26 March 2022 diff hist +22 m ROM Header No edit summary Tag: Visual edit
- 22:5822:58, 26 March 2022 diff hist −12 m ROM Header →Support by emulators Tag: Visual edit
- 22:5722:57, 26 March 2022 diff hist −201 ROM Header No edit summary Tag: Visual edit
- 22:5422:54, 26 March 2022 diff hist +4,608 ROM Header No edit summary Tag: Visual edit
- 22:1722:17, 26 March 2022 diff hist +37 ROM Header No edit summary Tag: Visual edit
- 22:1322:13, 26 March 2022 diff hist +287 ROM Header No edit summary Tag: Visual edit
- 21:5321:53, 26 March 2022 diff hist +355 ROM Header No edit summary Tag: Visual edit
- 19:0919:09, 26 March 2022 diff hist +838 ROM Header No edit summary Tag: Visual edit
- 18:5518:55, 26 March 2022 diff hist +1,794 N ROM Header Initial version Tag: Visual edit
- 18:3718:37, 26 March 2022 diff hist +13 m Game Pak No edit summary Tag: Visual edit
- 18:3618:36, 26 March 2022 diff hist +90 m Game Pak No edit summary Tag: Visual edit
14 November 2021
- 10:2010:20, 14 November 2021 diff hist +129 MIPS Interface No edit summary current
- 10:1910:19, 14 November 2021 diff hist +106 MIPS Interface No edit summary Tag: Visual edit: Switched
5 October 2021
- 23:0823:08, 5 October 2021 diff hist +45 Libdragon No edit summary current Tag: Visual edit
- 23:0723:07, 5 October 2021 diff hist +153 Libdragon No edit summary Tag: Visual edit
4 October 2021
- 18:1118:11, 4 October 2021 diff hist +7 Libdragon No edit summary Tag: Visual edit
- 18:1018:10, 4 October 2021 diff hist +1,065 Libdragon No edit summary
- 16:4216:42, 4 October 2021 diff hist 0 Libdragon No edit summary Tag: Visual edit
- 16:4016:40, 4 October 2021 diff hist +714 Libdragon No edit summary Tag: Visual edit
- 13:0313:03, 4 October 2021 diff hist +76 Libdragon No edit summary Tag: Visual edit
- 13:0113:01, 4 October 2021 diff hist +98 Libdragon No edit summary Tag: Visual edit
- 12:5912:59, 4 October 2021 diff hist +2,277 Libdragon Initial version Tag: Visual edit
30 August 2021
- 17:5117:51, 30 August 2021 diff hist +308 N Talk:RDRAM Interface Created page with "--~~~~ (SwapField[8:0] x Adr[19:11]) + ~SwapField[8:0]xAdr[28:20] Does this mean: (SwapField[8:0] & Adr[19:11]) | (~SwapField[8:0] & Adr[28:20]) That is, is the SwapField..."