Serial Interface

The Serial Interface (or SI) is one of multiple I/O interfaces in the RCP, which is used to communicate with the PIF-NUS and in turn, Joybus devices.

Memory mapped registers are used to configure the Serial Interface and initiate DMA reads and writes. The base address for these registers is, also known as SI_BASE. However, because all memory accesses in the CPU are made using virtual addresses, the following addresses must be offset appropriately. For non-cached reads/writes, add  to the address. As an example, to directly write to the SI_DRAM_ADDR register, use address.

= Registers = Table Notation: R = Readable bit W = Writable bit U = Undefined/Unused bit -n = Default value n at power on [x:y] = Specifies bits x to y, inclusively

0x0480 0000 - SI_DRAM_ADDR

 * U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0


 * RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
 * colspan="8" | DRAM_ADDR[23:16]
 * colspan="8" | DRAM_ADDR[23:16]


 * RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
 * colspan="8" | DRAM_ADDR[15:8]
 * colspan="8" | DRAM_ADDR[15:8]


 * RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
 * colspan="8" | DRAM_ADDR[7:0]
 * colspan="8" | DRAM_ADDR[7:0]

0x0480 0004 - SI_PIF_AD_RD64B
TODO

0x0480 0008 - SI_PIF_AD_WR4B
TODO

0x0480 0010 - SI_PIF_AD_WR64B
TODO

0x0480 0014 - SI_PIF_AD_RD4B

 * U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0


 * U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0


 * RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
 * - || - || - || - || - || colspan="3" | PIF_ADDR[10:8]
 * - || - || - || - || - || colspan="3" | PIF_ADDR[10:8]


 * RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || U-0 || U-0
 * colspan="6" | PIF_ADDR[7:2] || 0 || 0
 * colspan="6" | PIF_ADDR[7:2] || 0 || 0

This register is broken and doesn't work. It was meant to execute a DMA transfer with a  serial frame with PIF (to read 4 bytes from either PIF-ROM or PIF-RAM), but for some reason it does not work, and nothing is transferred. It is still documented here from completeness.

Notice that VR4300 can still do a 32-bit read from PIF-ROM/PIF-RAM using a direct memory read in the memory mapped space (physical address  -   and it will work correctly, though it will be a blocking read that will keep the VR4300 blocked as the serial transfer happens.

0x0480 0018 - SI_STATUS

 * U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0


 * U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0


 * U-0 || U-0 || U-0 || R-0 || U-0 || U-0 || U-0 || U-0
 * — || — || — || INTERRUPT || colspan="4" | DMA_STATE[3:0]
 * — || — || — || INTERRUPT || colspan="4" | DMA_STATE[3:0]


 * U-0 || U-0 || U-0 || U-0 || R-0 || R-0 || R-0 || R-0
 * colspan="4" | PCH_STATE[3:0] || style="font-size: 88%;" | DMA_ERROR || style="font-size: 88%;" | READ_PENDING || IO_BUSY || DMA_BUSY
 * colspan="4" | PCH_STATE[3:0] || style="font-size: 88%;" | DMA_ERROR || style="font-size: 88%;" | READ_PENDING || IO_BUSY || DMA_BUSY