Reality Display Processor/Interface

The RSP interface can be accessed in two ways:


 * From the VR4300. using memory mapped registers at physical address . However, because all memory accesses in the VR4300 are made using virtual addresses, it is normally used   to access the interface in the uncached segment.
 * From the RSP, using COP0 registers . These registers can be read / written using the opcodes   /   respectively. Notice that the first 8 registers (  -  ) are instead the RSP interface registers.

0x0410 0000 - DPC_START

 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
 * colspan=8|START[23:16]
 * colspan=8|START[23:16]


 * RW-? || RW-? || RW-? || RW-? || RW-? || RW- || RW-? || RW-?
 * colspan=8|START[15:0]
 * colspan=8|START[15:0]


 * RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
 * colspan=8|START[7:0]
 * colspan=8|START[7:0]

0x0410 0004 - DPC_END

 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
 * colspan=8|END[23:16]
 * colspan=8|END[23:16]


 * RW-? || RW-? || RW-? || RW-? || RW-? || RW- || RW-? || RW-?
 * colspan=8|END[15:0]
 * colspan=8|END[15:0]


 * RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
 * colspan=8|END[7:0]
 * colspan=8|END[7:0]

0x0410 0008 - DPC_CURRENT

 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
 * colspan=8|CURRENT[23:16]
 * colspan=8|CURRENT[23:16]


 * R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
 * colspan=8|CURRENT[15:0]
 * colspan=8|CURRENT[15:0]


 * R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
 * colspan=8|CURRENT[7:0]
 * colspan=8|CURRENT[7:0]

0x0410 000C - DPC_STATUS

 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || R-? || R-? || R-?
 * — || — || — || — || — || START_VALID || END_VALID || DMA_BUSY
 * — || — || — || — || — || START_VALID || END_VALID || DMA_BUSY


 * R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
 * READY || BUFFER_BUSY || PIPE_BUSY || TMEM_BUSY || START_GCLK || FLUSH || FREEZE_OR_CRASHED || SOURCE_IS_XBUS
 * READY || BUFFER_BUSY || PIPE_BUSY || TMEM_BUSY || START_GCLK || FLUSH || FREEZE_OR_CRASHED || SOURCE_IS_XBUS


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || W-? || W-?
 * — || — || — || — || — || — || CLR_CLOCK || CLR_BUFFER_BUSY
 * — || — || — || — || — || — || CLR_CLOCK || CLR_BUFFER_BUSY


 * W-? || W-? || W-? || W-? || W-? || W-? || W-? || W-?
 * CLR_PIPE_BUSY || CLR_TMEM_BUSY || SET_FLUSH || CLR_FLUSH || SET_FREEZE || CLR_FREEZE || SET_SOURCE || CLR_SOURCE
 * CLR_PIPE_BUSY || CLR_TMEM_BUSY || SET_FLUSH || CLR_FLUSH || SET_FREEZE || CLR_FREEZE || SET_SOURCE || CLR_SOURCE

0x0410 0010 - DPC_CLOCK

 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
 * colspan=8|CLOCK[23:16]
 * colspan=8|CLOCK[23:16]


 * R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
 * colspan=8|CLOCK[15:0]
 * colspan=8|CLOCK[15:0]


 * R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
 * colspan=8|CLOCK[7:0]
 * colspan=8|CLOCK[7:0]

0x0410 0014 - DPC_BUSY

 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
 * colspan=8|BUSY[23:16]
 * colspan=8|BUSY[23:16]


 * R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
 * colspan=8|BUSY[15:0]
 * colspan=8|BUSY[15:0]


 * R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
 * colspan=8|BUSY[7:0]
 * colspan=8|BUSY[7:0]

0x0410 0018 - DPC_PIPE_BUSY

 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
 * colspan=8|PIPE_BUSY[23:16]
 * colspan=8|PIPE_BUSY[23:16]


 * R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
 * colspan=8|PIPE_BUSY[15:0]
 * colspan=8|PIPE_BUSY[15:0]


 * R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
 * colspan=8|PIPE_BUSY[7:0]
 * colspan=8|PIPE_BUSY[7:0]

0x0410 001C - DPC_TMEM_BUSY

 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
 * colspan=8|TMEM_BUSY[23:16]
 * colspan=8|TMEM_BUSY[23:16]


 * R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
 * colspan=8|TMEM_BUSY[15:0]
 * colspan=8|TMEM_BUSY[15:0]


 * R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
 * colspan=8|TMEM_BUSY[7:0]
 * colspan=8|TMEM_BUSY[7:0]

0x0420 0000 - DPS_TBIST

 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || R-? || R-? || R-?
 * — || — || — || — || — || colspan=3|FAIL[7:5]
 * — || — || — || — || — || colspan=3|FAIL[7:5]


 * R-? || R-? || R-? || R-? || R-? || RW-? || RW-? || RW-?
 * colspan=5|FAIL[4:0] || DONE || GO || CHECK
 * colspan=5|FAIL[4:0] || DONE || GO || CHECK

0x0420 0004 - DPS_TEST_MODE

 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || RW-?
 * — || — || — || — || — || — || — || ENABLE
 * — || — || — || — || — || — || — || ENABLE

0x0420 0008 - DPS_BUFTEST_ADDR

 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
 * — || colspan=7| ADDRESS[6:0]
 * — || colspan=7| ADDRESS[6:0]

0x0410 000C - DPS_BUFTEST_DATA

 * RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
 * colspan=8|DATA[31:24]
 * colspan=8|DATA[31:24]


 * RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
 * colspan=8|DATA[23:16]
 * colspan=8|DATA[23:16]


 * RW-? || RW-? || RW-? || RW-? || RW-? || RW- || RW-? || RW-?
 * colspan=8|DATA[15:0]
 * colspan=8|DATA[15:0]


 * RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
 * colspan=8|DATA[7:0]
 * colspan=8|DATA[7:0]