RDRAM Interface

The RDRAM Interface (or RI) is one of multiple I/O interfaces in the RCP. It acts as a controller for the RDRAM channel to which one or more RDRAM modules are connected. It converts memory accesses from the system into RDRAM protocol commands for the RDRAM bus. The RI integrates a RDRAM ASIC Cell (or RAC) in order to take care of the low level details of the RDRAM bus. Further details about such a RAC can be found in datasheets for similar RACs (however not necessarily the same version used by the N64).

There are two sets of memory mapped registers for RDRAM configuration. One set is specifically for writing to or reading from the configuration registers in one or all individual RDRAM module(s). The other set, defined in the next section, configure this RDRAM interface. Refer to Memory map for the full map, including all RDRAM-related segments.

The base address for these registers is, also known as RI_BASE. However, because all memory accesses in the CPU are made using virtual addresses, the following addresses must be offset appropriately. For non-cached reads/writes, add  to the address. As an example, to directly write to the RI_MODE register, use address.

Some information is available in US6593929.pdf in paragraph "Example Memory Controller/Interface Registers" and associated figures (37A-H).

= Registers = Table Notation: R = Readable bit W = Writable bit U = Undefined/Unused bit -n = Default value n at boot -? = Unknown default value [x:y] = Specifies bits x to y, inclusively

0x0470 0000 - RI_MODE

 * U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0


 * U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0


 * U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0


 * U-0 || U-0 || U-0 || U-0 || RW-1 || RW-1 || RW-? || RW-?
 * — || — || — || — || STOP_R || STOP_T || colspan="2" | OP_MODE[1:0]
 * — || — || — || — || STOP_R || STOP_T || colspan="2" | OP_MODE[1:0]

0x0470 0004 - RI_CONFIG

 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
 * — || AutoCC || colspan="6" | CC [5:0]
 * — || AutoCC || colspan="6" | CC [5:0]

READ?/WRITE: [6]     Enable/Disable automatic current calibration from controller. It selects whether the the value CC[5:0] will be written to current control register (AutoCC=0), or an internally generated value (AutoCC=1). [5:0]   Current Control Input. The value to be loaded into current control register when autoCC is disabled.

0x0470 0008 - RI_CURRENT_LOAD

 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?

WRITE: TOVERIFY: Any write to this register will load a new value into the current control register. The value loaded depends on the value of AutoCC. See RI_CONFIG for details. TOVERIFY: When AutoCC=1, a sufficient delay should be observed to let CC autocalibration stabilize.

0x0470 000C - RI_SELECT

 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
 * colspan="4" | TSEL [3:0] || colspan="4" | RSEL [3:0]
 * colspan="4" | TSEL [3:0] || colspan="4" | RSEL [3:0]

0x0470 0010 - RI_REFRESH

 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || RW-? || RW-? || RW-? || RW-? || RW-?
 * — || — || — || colspan="2" | MultiBank[??:0] || Opt || En || Bank
 * — || — || — || colspan="2" | MultiBank[??:0] || Opt || En || Bank


 * RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
 * colspan="8" | DirtyRefreshDelay [7:0]
 * colspan="8" | DirtyRefreshDelay [7:0]


 * RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
 * colspan="8" | CleanRefreshDelay [7:0]
 * colspan="8" | CleanRefreshDelay [7:0]

0x0470 0014 - RI_LATENCY

 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?


 * U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?

TODO: remaining registers

= Memory addressing = RI translate memory accesses in the range  -   into suitable RDRAM protocol packets with proper command type and 36 bit address. See RDRAM addressing paragraph for details about how 36bit addresses are interpreted.

Address conversion done by RI (TOVERIFY):

Examples :

Assuming a standard RDRAM configuration of 4x2x9Mbit RDRAM each with IdField = 2*k for module k = 0..3 and SwapField = 0 for all modules (eg. no address swapping, Adr = AdrS).


 * Reading at address 0x003A BCDE, gives the following Adr[35:20] = 3, Adr[19:0] = 0xABCDE, BCastRWrite = 0. Since we have 2x9Mbit modules, Adr[20] is ignored for Id matching and therefore RDRAM with IdField == 2 gives a match. This means RDRAM module 1 will be read at address 0x1ABCDE.
 * Writing at address 0x03F0 0808, gives Adr[35:20] = 2, Adr[19:0] = 8, BCastRWrite = 0. Which means writing to RDRAM module 1 delay register.
 * Writing at address 0x03F8 0008, gives BCastRWrite = 1, Adr[19:0] = 8. Which means broadcast writing to all RDRAM modules delay registers.

Remarks :


 * Early version of RCP reserved fewer bits for RDRAM register address (eg. Adr[35:20] = (address >> 9) & 0x3FF; Adr[19:0] = address & 0x1FF) which didn't allow to access RDRAM register 128 (Row register) which is at offset 0x200.
 * The presented address map supports up to 32x 2x9Mbit RDRAM modules. However, a maximum of 8MiB is accessible with the IPL3 in all commercial carts.
 * Standard DRAM initialization only supports up to 8 modules, but can mix 2x9Mbit and 1x9Mbit modules. In that case, 2x9Mbit modules are placed before 1x9Mbit modules.
 * Standard DRAM initialization procedure, doesn't make use of address swapping feature, even though it may increase DRAM hit rate according to datasheets.
 * Register-space addresses duplicates the content between Adr[28:20] and Adr[19:11] to not be affected by RDRAM address swapping features. Indeed, whereas address swapping is desirable for RDRAM memory to benefit from row internal row caching, registers won't benefit from the swapping and would complicate usage of registers in such a case.