MIPS Interface

The MIPS Interface (or MI) is one of multiple I/O interfaces in the RCP. It is the interface between the RCP and the VR4300 CPU, primarily used for enabling/disabling interrupts and checking their status.

Memory mapped registers are used to configure the MIPS Interface. The base address for these registers is, also known as MI_BASE. However, because all memory accesses in the CPU are made using virtual addresses, the following addresses must be offset appropriately. For non-cached reads/writes, add  to the address. As an example, to directly write to the MI_MODE register, use address.

Note that some of these registers have different behavior when writing to them, than when reading from them. When writing to a register that has Set and Clear bits, write a 1 on the desired bit. Writing 0's have no effect. Behavior is unknown when writing 1's to both Set and Clear bits in a pair at the same time.

Accesses beyond  are mirrored, so only the first four bits are taken into account for address decoding.

= Registers = Table Notation: R = Readable bit W = Writable bit U = Undefined/Unused bit -n = Default value n at power on [x:y] = Specifies bits x to y, inclusively

0x0430 0000 - MI_MODE

 * U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0


 * U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0


 * U-0 || U-0 || W-0 || W-0 || W-0 || W-0 || RW-0 || RW-0
 * — || — || colspan="6" | Details Below
 * — || — || colspan="6" | Details Below


 * RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || U-0 || RW-0 || RW-0
 * Details Below || colspan="7" | INIT_LENGTH[6:0]
 * Details Below || colspan="7" | INIT_LENGTH[6:0]

READ:                            WRITE: [13]  —                          [13]   Set RDRAM register mode [12]  —                          [12]   Clear RDRAM register mode [11]  —                          [11]   Clear DP interrupt [10]  —                          [10]   Set ebus test mode [9]   RDRAM register mode        [9]    Clear ebus test mode [8]   ebus test mode             [8]    Set init mode [7]   init mode                  [7]    Clear init mode [6:0] init length                [6:0]  init length

0x0430 0004 - MI_VERSION

 * R-0 || R-0 || R-0 || R-0 || R-0 || R-0 || R-? || R-?
 * colspan="8" | RSP_VERSION[7:0]
 * colspan="8" | RSP_VERSION[7:0]


 * R-0 || R-0 || R-0 || R-0 || R-0 || R-0 || R-? || R-?
 * colspan="8" | RDP_VERSION[7:0]
 * colspan="8" | RDP_VERSION[7:0]


 * R-0 || R-0 || R-0 || R-0 || R-0 || R-0 || R-? || R-?
 * colspan="8" | RAC_VERSION[7:0]
 * colspan="8" | RAC_VERSION[7:0]


 * R-0 || R-0 || R-0 || R-0 || R-0 || R-0 || R-? || R-?
 * colspan="8" | IO_VERSION[7:0]
 * colspan="8" | IO_VERSION[7:0]

Extra Details:
 * It is not known for certain the full extent of values that can exist here. Most consoles report, though emulators and other docs seem to mention other similar values such as   or  . iQue retail consoles report  . Testing should be performed on all revisions of the N64 motherboard and development systems. Results will be listed here.

0x0430 0008 - MI_INTERRUPT

 * U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0


 * U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0


 * U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0


 * U-0 || U-0 || R-0 || R-0 || R-0 || R-0 || R-0 || R-0
 * — || — || DP || PI || VI || AI || SI || SP
 * — || — || DP || PI || VI || AI || SI || SP

0x0430 000C - MI_MASK

 * U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0


 * U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0


 * U-0 || U-0 || U-0 || U-0 || W-0 || W-0 || W-0 || W-0
 * — || — || — || — || colspan="4" | Details Below
 * — || — || — || — || colspan="4" | Details Below


 * W-0 || W-0 || RW-0 || RW-0 || RW-0 || U-0 || RW-0 || RW-0
 * colspan="8" | Details Below
 * colspan="8" | Details Below

READ:                            WRITE: [11]  —                          [11]   Set DP Interrupt Mask [10]  —                          [10]   Clear DP Interrupt Mask [9]   —                          [9]    Set PI Interrupt Mask [8]   —                          [8]    Clear PI Interrupt Mask [7]   —                          [7]    Set VI Interrupt Mask [6]   —                          [6]    Clear VI Interrupt Mask [5]   DP Interrupt Mask          [5]    Set AI Interrupt Mask [4]   PI Interrupt Mask          [4]    Clear AI Interrupt Mask [3]   VI Interrupt Mask          [3]    Set SI Interrupt Mask [2]   AI Interrupt Mask          [2]    Clear SI Interrupt Mask [1]   SI Interrupt Mask          [1]    Set SP Interrupt Mask [0]   SP Interrupt Mask          [0]    Clear SP Interrupt Mask