EverDrive-64 v3

The EverDrive-64 v3 is a flash cart made by Krikzz.

Basic information
ROM: Max 64MiB

RTC: supported

Save: 4ki/16ki bit EEPROM, 32KiB/128KiB SRAM, 128KiB Flash

USB Serial: 512-bytes block read-write

SD: SD or SDHC

Registers
All registers must be accessed by 32bit word, but it seems only lower 16bits are valid.

High 16bits of all registers seems REG_STATUS on read.

Base PI address for registers is  (Cartridge Domain 2, SRAM area +0x40000)

You should access these registers from CPU through no-cached segment, i.e., ex. for REG_KEY.

0x08040000 (REG_CFG)
Read/Write

0x08040004 (REG_STATUS)
Read only

0x08040008 (REG_DMA_LEN)
Write only

0x0804000C (REG_DMA_RAM_ADDR)
Write only

0x08040010 (REG_MSG)
Read/Write

It seems generic 16bit storage.

In ED64 OS v2.12, this register used as following:

0x08040014 (REG_DMA_CFG)
Write only Note that above table numbers are value, not "bit from lsb".

You must set REG_DMA_LEN and REG_DMA_RAM_ADDR before writing this register.

0x08040018 (REG_SPI)
Read/Write Writing value to this invokes clock CLK on SD card.

You should also write this to read. (write value is ignored)

0x0804001C (REG_SPI_CFG)
Read/Write

0x08040020 (REG_KEY)
Write only Note that you should dummy-read REG_CFG before writing to REG_KEY, or it may be ignored (glitch).

0x08040024 (REG_SAV_CFG)
Read/Write But this register should be treated as a value not bitfields (like REG_DMA_CFG)

0x08040028 (REG_SEC)
Write only?

0x0804002C (REG_VER)
Read only ex. 0x0304 for Firmware v3.04

0x08040030 (I2C/RTC)
Read/Write You must set DAT=1 before read, or you'll get always DAT=0 (because of I2C's open-drain).

DS1337 (RTC) at address 0x58.

0x08040040 (REG_CFG_CNT)
Read/Write on REG_CFG&1==0

SDRAM must be disabled (REG_CFG & 1 must be zero).

0x08040044 (REG_CFG_DAT)
Write only? on REG_CFG&1==0

SDRAM must be disabled (REG_CFG & 1 must be zero).

0x08040048 (REG_MAX_MSG)
Read/Write on REG_CFG&1==0

SDRAM must be disabled (REG_CFG & 1 must be zero).

0x0804004C (REG_CRC)
Read only? on REG_CFG&1==0 SDRAM must be disabled (REG_CFG & 1 must be zero).

This register seems not related to "Cyclic Redundancy Check".

0x08040050
Write only? on REG_CFG&1==0

TBA

SDRAM must be disabled (REG_CFG & 1 must be zero).

0x08040054
Write only on REG_CFG&1==0 ?

TBA

SDRAM must be disabled (REG_CFG & 1 must be zero).

ED64 Boot ROM Header
You can read boot ROM header by:


 * set  (disable SDRAM)
 * read from cart usually (by  etc, or use PI DMA)

They are, of course, big endian.

Common Code
Before communication, you must enable ED64 registers.

Sending Data to the Host
You should transfer data from RDRAM to some area on cart "ROM" area first, then use Cart->USB DMA on ED64.

Reading Data from the Host
You should use USB->Cart DMA on ED64 first, then transfer data from cart ROM area to RDRAM.

At least on HW v3.04, it seems that USB->Cart transfer is done at 16-bit halfwords. If received data is NOT aligned at 16-bit, that last byte will be lost. Of course if received data is shorter than "len", DMA will be timed out, cause waiting ~500ms to DMA done until timeout, so you should send data from host by 512 bytes block for faster communication.