Peripheral Interface

The Peripheral Interface (or PI, or Parallel Interface) is one of multiple I/O interfaces in the RCP, which is used to communicate with game cartridges or other devices connected to either the cartridge port or expansion port on the bottom of the console. (e.g. 64DD)

Memory mapped registers are used to configure the Peripheral Interface and initiate DMA reads and writes. The base address for these registers is, also known as PI_BASE. However, because all memory accesses in the CPU are made using virtual addresses, the following addresses must be offset appropriately. For non-cached reads/writes, add  to the address. As an example, to directly write to the PI_DRAM_ADDR register, use address.

= Registers = Table Notation: R = Readable bit W = Writable bit U = Undefined/Unused bit -n = Default value n at power on [x:y] = Specifies bits x to y, inclusively

0x0460 0000 - PI_DRAM_ADDR

 * U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0


 * RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
 * colspan="8" | DRAM_ADDR[23:16]
 * colspan="8" | DRAM_ADDR[23:16]


 * RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
 * colspan="8" | DRAM_ADDR[15:8]
 * colspan="8" | DRAM_ADDR[15:8]


 * RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
 * colspan="8" | DRAM_ADDR[7:0]
 * colspan="8" | DRAM_ADDR[7:0]

TODO

= Physical Bus Pinout = The PI Bus is a Bi-directional and MUX'ed interface where there is a 16bit data path to the Rom, 64DD, Flash Ram and SRAM ram chips is used to send both the wanted address and data to and from the RCP. This is not to be confused with the serial EEPROM, CIC and RTC (real time clock) chips that go through the SI interface and PIF chip via the cartridge port as well.

= Mapped Domains = Reads or writes to these physical memory segments are mapped to the PI bus. For example, attempting to read from address 0x10000000 will cause a PI bus read at address 0x10000000. This means that even if a cartridge/device has data stored at addresses outside these segments, software running on the console will not be able to access it. Historically, each segment was intended for a different purpose. Game cartridges always expect software to read from the  segment in order to access the game's ROM data. Custom hardware and software could potentially utilize any or all of these segments in different/unintended ways. Some flashcarts are known to use  for special features or debugging. The domain number determines which PI timing/page settings apply to which memory segments. Thus, reads/writes to the cartridge ROM segment use the settings for domain 1. It's possible to configure certain characteristics of the communication protocol: latency, pulse-width, release, and page-size. Domain 1 is set automatically during IPL2, by reading the first 4 bytes of the cartridge/device that's connected to the console at boot. Both domains can be configured by software at any time.

= Parallel Interface Registers = 0x0460 0000 to 0x046F FFFF  Address range:

Constant Read:


=Aligned DMA Transfer= An aligned DMA transfer is when the PI_DRAM_ADDR_REG is set to a 64bit (8byte) aligned address. The PI_CART_ADDR_REG can be any 16bit (2Byte) value as will transfer from that offset to RDRAM.

The PI_RD_LEN_REG and PI_WR_LEN_REG can be any length, as long as it is a 2 byte aligned amount (more testing is to be done on this to confirm this)

= Unaligned DMA transfer = An un-aligned ROM dma transfer is when you use the PI_DRAM_ADDR_REG and not set it as a 8 Byte aligned address and use variable PI_RD_LEN_REG and PI_WR_LEN_REG lengths.

The following rules are based on assumptions via the created test ROMs by Krom, Mazamars312 and Lemmy (https://github.com/PeterLemon/N64/tree/master/CPUTest/DMAAlignment-PI-cart)