MIPS III instructions

The NEC VR4300 uses an instruction set that is nearly identical to that of the MIPS III Instruction Set Architecture (ISA). While the instruction set is explained in detail in the VR4300 datasheet, this article serves as a reformatted reference for those same instructions, including any quirks or additional reminders that are useful when programming something for the N64.

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= Instruction Notation Key =

= CPU Instruction Set = Every instruction has a 32-bit instruction word that the CPU uses to identify the instruction and any arguments used in it. The upper 6 bits is the instruction's opcode, however some instructions use additional constant bits to further define the operation. For example, the SPECIAL opcode is used for numerous instructions including ADD, SUB, AND, BREAK, and more.

Typically an assembler will be used when programming in order to format the proper instruction word, when generating a ROM file. Most developers can safely ignore the instruction word column entirely.

''However, most assemblers implement branch instructions differently! Instead of an offset value, they usually require the use of a label or absolute address.''

ADD
Format: ADD rd, rs, rt Description::

Exceptions::

ADDI
Format: ADDI rt, rs, immediate Description::

Exceptions::

= FPU Instruction Set = The floating point unit (FPU) is contained within the VR3400 microprocessor and handles floating point operations.

= Pseudo-Instructions = Many assemblers, regardless of architecture, will add additional instructions to assist developers. This table shows the instructions added by the bass assembler, which is commonly used to develop N64 ROMs.